• Journal of Power Electronics
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• v.16 no.4
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• pp.1316-1323
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• 2016

Multilevel inverters (MLIs) have been preferred over conventional two-level inverters due to their inherent properties such as reduced harmonic distortion, lower electromagnetic interference, minimal common mode voltage, ability to synthesize medium/high voltage from low voltage sources, etc. On the other hand, they suffer from an increased number of switching devices, complex gate pulse generation, etc. This paper develops an ingenious symmetrical MLI topology, which consumes lesser component count. The proposed level dependent sources concoction multilevel inverter (LDSCMLI) is basically a multilevel dc link MLI (MLDCMLI), which first synthesizes a stepped dc link voltage using a sources concoction module and then realizes the ac waveform through a conventional H-bridge. Seven level and eleven level versions of the proposed topology are simulated in MATLAB r2010b and prototypes are constructed to validate the performance. The proposed topology requires lesser components compared to recent component reduced MLI topologies and the classical topologies. In addition, it requires fewer carrier signals and gate driver circuits.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.48 no.10
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• pp.544-554
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• 1999

Multi-level inverters are now receiving widespread interest form the industrial drives for high power variable speed applications. Especially, for the high power variable speed applications, a diode clamped multi-level inverter has been widely used. However, it has the inherent problem that the voltage of the link capacitors fluctuates. This paper describes a voltage control scheme effectively to suppress the DC-link potential fluctuation for a diode clamped four-level inverter. The current to flow from/into the each link capacitor is analyzed and the operation limit is obtained when a conventional SVPWM is used. To overcome the operation limit, a modified carrier-based SVPWM is proposed. Various simulation and experiment results are presented to verify the proposed voltage control scheme for DC-link voltage balancing.

• Proceedings of the KIEE Conference
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• 1995.07a
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• pp.360-364
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• 1995

A zero voltage switching (ZVS) three level resonant pole inverter is presented for high power GTO inverters. The concept of auxiliary resonant commutated pole(ARCP) for two level inverter is extended to the three level inverter. The proposed auxiliary commutation circuit consists of one resonant inductor and two bi-directional switches, which provides ZVS condition to the main devices without increasing device voltage or current stresses. The auxiliary device operates with zero current switching(ZCS) which enables use of the low cost thyristors. The proposed circuit can handle higher voltage and higher power(1-10MVA) comparing to the two level one. Operation and analysis of the proposed circuit are illustrated. Experimental results with 10 KW, 4 kHz prototype are presented to verify the principle of operation.

• The Transactions of the Korean Institute of Power Electronics
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• v.6 no.5
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• pp.432-437
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• 2001

This paper describes a new developed 3.3KV/4MW class three-level Voltage Source Inverter(VSI), which is equipped with IIMS(Inverter Information Management System) based on the world wide web and with the Virtual operation simulator. The algorithm for motor control is the stator oriented Direct Torque Control(DTC), which works without speed sensor and gives the physically fastest dynamic response. The IIMS have the functions of operation monitoring and data managements. Virtual operation simulator can analyze and tune the system characteristics without main power. Now, this system is under the field test to verify the confidence.

• The Transactions of the Korean Institute of Power Electronics
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• v.25 no.4
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• pp.319-328
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• 2020

The recent use of distributed power generation systems constructed with DC-DC converters has become extremely popular owing to the rising need for environment friendly energy generation power systems. In this study, a new single-phase five-level inverter for off-grid applications constructed with a multilevel DC-DC step-up converter is proposed to boost a low-level DC voltage (36 V-64 V) to a high-level DC bus (380 V) and invert and connect them with a single-phase 230 V rms AC load. Compared with other traditional multilevel inverters, the proposed five-level inverter has a reduced number of switching devices, can generate high-quality power with lower THD values, and has balanced voltage stress for DC capacitors. Moreover, the proposed topology does not require multiple DC sources. Finally, the performance of the proposed topology is presented through the simulation and experimental results of a 400 W hardware prototype.

• The Transactions of the Korean Institute of Power Electronics
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• v.19 no.4
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• pp.376-382
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• 2014

This paper proposes the pulse width modulation (PWM) control strategy for low-speed operation in the three-level neutral-point-clamped (NPC) inverters based on the bootstrap gate drive circuit. As a purpose of the cost reduction, several papers have paid attention to the bootstrap circuit applied to the three-level NPC inverter. However, the bootstrap gate driver IC cannot generate the gate signal to the IGBT for low-speed operation, because the bootstrap capacitor voltage decreases under the threshold level. For low-speed operation, the dipolar and partial-dipolar modulations can be the effective solution. However, these modulations have drawbacks in terms of the switching loss and THD. Therefore, this paper proposes the PWM control strategy to operate the inverter at low-speed and to minimize the switching loss and harmonics. The experimental results are presented to verify the validity on the proposed method.

• Journal of Power Electronics
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• v.15 no.4
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• pp.910-919
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• 2015

The use of a PV grid-connected inverter with non-isolated topology and without a transformer is good for improving conversion efficiency; however, this inverter has become increasingly complicated for eliminating leakage current. To simplify the complicated architecture of traditional three-level dual buck inverters, a new dual Buck three-level PV grid-connected inverter topology is proposed. In the proposed topology, the voltage on the grounding stray capacitor is clamped by large input capacitors and is equal to half of the bus voltage; thus, leakage current can be eliminated. Unlike in the traditional topology, the current in the proposed topology passes through few elements and does not flow through the body diodes of MOSFET switches, resulting in increased efficiency. Additionally, a multi-loop control method that includes voltage-balancing control is proposed and analyzed. Both simulation and experimental results are demonstrated to verify the proposed structure and control method.

• Proceedings of the KIPE Conference
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• 2002.11a
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• pp.171-174
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• 2002

This paper deals with a novel method in order to analyze the harmonic characteristics in the multi-level inverter. Generally, the magnitude of harmonic components is different according to the carrier PWM techniques, modulation Index(Mi), and the level of multi-level inverter The previous papers analyzed the harmonic characteristics from the viewpoint of the space vector. Hence, the calculation of the harmonic vector becomes difficult and complex in 4-level or more than S-level. However, the proposed method of this paper reduced an amount of calculation and simplified the process of calculation by using the relationship between reference voltage and output phase voltage to load neutral. This paper analyzed the harmonic and it is applied to the multi-carrier PWM techniques in 5- level and other-level of cascaded inverter system.

• Journal of Electrical Engineering and Technology
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• v.13 no.4
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• pp.1528-1538
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• 2018

In this paper, configuration of $1-{\phi}$ seven-level boost DC-link cascade based reversing voltage multilevel inverter (BDCLCRV MLI) is proposed for uninterrupted power supply (UPS) applications. It consists of three level boost converter, level generation unit and full bridge circuit for polarity generation. When compared with conventional boost cascaded H-bridge MLI configurations, the proposed system results in reduction of DC sources, reduced power switches and gate drive requirements. Inverter switching is accomplished by providing appropriate switching angles that is generated by any optimization switching angle techniques. Here, round modulation control (RMC) method is taken as the optimization method and switching angles are derived and the same is compared with various switching angles methods i.e., equal-phase (EP) method, and half-equal-phase (HEP) method which results in improved quality of obtained AC power with lowest total harmonic distortion (THD). Reduction in DC sources and switch count makes the system more cost effective. A simulation and prototype model of $1-{\phi}$ seven-level BDCLCRV MLI system is developed and its performance is analyzed for various operating conditions.

• International Journal of Air-Conditioning and Refrigeration
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• v.6
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• pp.27-35
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• 1998

An experimental study was performed to investigate the optimum cycle of an inverter heat pump as a function of frequency. The performance of the inverter heat pump with the rated cooling capacity of 4,141 W(3,550kcal/h) was measured with a variation of frequency, indoor and outdoor temperature, and length of capillary tube in the psychrometric test room. As a base case, the inverter heat pump with the standard capillary length of l,000mm(optimum size for the frequency of 60Hz) and ASHRAE Test condition "A" was tested by varying frequency from 30Hz to 80Hz. Then, the optimum cycles were investigated by varying the length of capillary tube at each frequency level of 30, 60 and 80Hz. Based on the experimental data, the change of system characteristics between the optimum and the base case were analyzed for each selected frequency level. Generally, for low frequency level(30Hz), the longer length of the capillary tube compared with the standard size showed the higher energy efficiency ratio(EER), while for high frequency level(80Hz) the shorter length of the capillary tube showed the higher EER.