• JSTS:Journal of Semiconductor Technology and Science
• /
• 제10권1호
• /
• pp.1-10
• /
• 2010

This paper proposes a two-phase clocked adiabatic static CMOS logic (2PASCL) circuit that utilizes the principles of adiabatic switching and energy recovery. The low-power 2PASCL circuit uses two complementary split-level sinusoidal power supply clocks whose height is equal to $V_{dd}$. It can be directly derived from static CMOS circuits. By removing the diode from the charging path, higher output amplitude is achieved and the power consumption of the diode is eliminated. 2PASCL has switching activity that is lower than dynamic logic. We also design and simulate NOT, NAND, NOR, and XOR logic gates on the basis of the 2PASCL topology. From the simulation results, we find that 2PASCL 4-inverter chain logic can save up to 79% of dissipated energy as compared to that with a static CMOS logic at transition frequencies of 1 to 100 MHz. The results indicate that 2PASCL technology can be advantageously applied to low power digital devices operated at low frequencies, such as radio-frequency identifications (RFIDs), smart cards, and sensors.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• 제40권10호
• /
• pp.52-62
• /
• 2003

This paper discusses ternary logic gate, ternary D flip-flop, and ternary four-digit parallel input/output register. The ternary logic gates consist of n-channel pass transistors and neuron MOS(νMOS) threshold inverters on voltage mode. They are designed with a transmission function using threshold inverter that are in turn, designed using Down Literal Circuit(DLC) that has various threshold voltages. The νMOS pass transistor is very suitable gate to the multiple-valued logic(MVL) and has the input signal of the multi-level νMOS threshold inverter. The ternary D flip-flop uses the storage element of the ternary data. The ternary four-digit parallel input/output register consists of four ternary D flip-flops which can temporarily store four-digit ternary data. In this paper, these circuits use 3.3V low power supply voltage and 0.35m process parameter, and also represent HSPICE simulation result.

• Journal of Power Electronics
• /
• 제11권4호
• /
• pp.471-478
• /
• 2011

This paper addresses the establishment of a kVA-range plug-in hybrid electrical vehicle (PHEV) integration test platform and associated issues. Advancements in battery and power electronic technology, hybrid vehicles are becoming increasingly dependent on the electrical energy provided by the batteries. Minimal or no support by the internal combustion engine may result in the vehicle being occasionally unable to recharge the batteries during highly dynamic driving that occurs in urban areas. The inability to sustain its own energy source creates a situation where the vehicle must connect to the electrical grid in order to recharge its batteries. The effects of a large penetration of electric vehicles connected into the grid are still relatively unknown. This paper presents a novel methodology that will be utilized to study the effects of PHEV charging at the sub-transmission level. The proposed test platform utilizes the power hardware-in-the-loop (PHIL) concept in conjunction with high-fidelity PHEV energy system simulation models. The battery, in particular, is simulated utilizing a real-time digital simulator ($RTDS^{TM}$) which generates appropriate control commands to a power electronics-based voltage amplifier that interfaces via a LC-LC-type filter to a power grid. In addition, the PHEV impact is evaluated via another power electronic converter controlled through $dSPACE^{TM}$, a rapid control systems prototyping software.

• Journal of IKEEE
• /
• 제25권2호
• /
• pp.399-407
• /
• 2021

This paper proposes the DC-link voltage design method of Type 4 wind turbine that minimizes power loss and satisfies the High Voltage Ride Through(HVRT) function requirements of the transmission system operator. The Type 4 wind turbine used for large-capacity offshore wind turbine consists of the Back-to-Back converter in which the converter linked to the power grid and the inverter linked to the wind turbine share the DC-link. When the grid high voltage fault occurs in the Type 4 wind turbine, if the DC-link voltage is insufficient compared to the fault voltage level, the current controller of the grid-side converter can't operate smoothly due to over modulation. Therefore, to satisfy the HVRT function, the DC-link voltage should be designed based on the voltage level of high voltage fault. However, steady-state switching losses increase further as the DC-link voltage increases. Therefore, the considerations should be included for the loss to be increased when the DC-link voltage is designed significantly. In this paper, the design method for the DC-link voltage considered the fault voltage level and the loss is explained, and the validity of the proposed design method is verified through the HVRT function simulation based on the PSCAD model of the 2MVA Type 4 wind turbine.

• The Transactions of the Korean Institute of Power Electronics
• /
• 제22권3호
• /
• pp.240-248
• /
• 2017

This paper describes the development of a powertrain for a 20 kW experimental electric vehicle using a surface-mounted permanent magnet synchronous motor (SPMSM) and its application to a test vehicle. Two 10 kW SPMSMs are used in the powertrain, and two-level inverters are developed by using IGBTs to derive these motors. To control the SPMSM, a control board based on a TMS320F28335 DSP module, which has fast arithmetic function and floating point operator, is used. We develop a 100 V/40 A battery pack, which includes $32{\times}4$ LiFePO4 battery cells using commercial BMS. A commercial on-board charger with 220 V (AC) input and 100 V (DC) and 18 A output is used to charge the battery pack. The performance of the developed vehicle, such as acceleration availability, maximum speed, and maximum power, is estimated based on vehicle dynamics and verified through experiments.

• Journal of Power Electronics
• /
• 제4권1호
• /
• pp.1-11
• /
• 2004

A stable adaptive sensorless speed controller for three-level inverter fed induction motor direct torque control (DTC) system using the radial-basis function network (RBFN) is presented in this paper. Torque ripple in the DTC system for high power induction motor could be drastically reduced with the foregoing researches of switching voltage selection and torque ripple reduction algorithms. However, speed control performance is still influenced by the inherent uncertainty of the system such as parametric uncertainty, external load disturbances and unmodeled dynamics, and its exact mathematical model is much difficult to be obtained due to their strong nonlinearity. In this paper, the inherent uncertainty is approximated on-line by the RBFN, and an additional robust control term is introduced to compensate for the reconstruction error of the RBFN instead of the rich number of rules and additional updated parameters. Control law for stabilizing the system and adaptive laws for updating both of weights in the RBFN and a bounding constant are established so that the whole closed-loop system is stable in the sense of Lyapunov, and the stability proof of the whole control system is presented. Computer simulations as well as experimental results are presented to show the validity and effectiveness of the proposed system.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• 제41권4호
• /
• pp.51-58
• /
• 2004

Push-pull structure with balun transformer is presented for load modulation technique which improves the overall efficiency of power amplifier Under the assumption that output impedance of fumed-off amplifier is high, conventional Doherty amplifier is composed of impedance inverter and peaking amplifier, of which operation is controlled by the input power level. In many case, however, impedance of 'off'amplifier is very low due to matching network or parasitic output capacitance. This paper introduces novel load modulation technique which uses low output impedance of 'off'amplifier. Experimental results show that good linearity and efficient!'enhancement of the proposed push-pull structure

• Journal of Welding and Joining
• /
• 제19권6호
• /
• pp.622-629
• /
• 2001

The aim of this experiment is to establish the method that obtains symmetrically two nuggets in microresistance series spot welding. The sheets of austenite stainless steel STS304 applied to various electronic parts were experimented by the inverter welding power source of polarity controllable type and by the twin head for left and right electrode force to be controlled separately. The experimental results were obtained as follows : 1) When series spot welding was carried out by DC 1 pulse as welding current with same electrode force at left and right, the asymmetry of nuggets was resulted from the larger nugget of the (-) pole because of the Peltier effect. The dynamic resistance of weld spot at left and right was appeared differently according to the growth of nuggets. 2) When AC 1 cycle by welding power source of polarity controllable type was applied, the nuggets were almost symmetrically formed. 3) In a twin head, if the electrode force of (-) pole was larger than that of (+) pole, the diameters of two nuggets became to same. It was confirmed that the dynamic resistance of (-) pole was decreased to the same level as it of (+) pole. 4) Although the forces of left and right electrode were same, and only DC 1 pulse was applied, symmetric nuggets were obtained if the conductivity of (+) pole was lower than it of (-) pole.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• 제18권4호
• /
• pp.602-610
• /
• 1993

The DDA of new active element and the DDA differential integrator are designed. The DDA can be improved matching problems of external elements in op-amp application circuits. The design of DDA is used the transconductance element, differential pair and $2{\mu}m$ design rule. In order to evaluate the performance of the CMOS DDA, we simulated the DDA voltage inverter and the DDA level shifter using the designed CMOS DDA. Furthermore, the grounded resistor and the differential integrator is designed using the CMOS DDA and we found that its characteristics are agreed to OP-AMP differential integrator's. We performed the layout of the CMOS DDA and DDA differential integrator with MOSIS $2{\mu}m$ CMOS technology.

• Journal of Digital Convergence
• /
• 제11권4호
• /
• pp.229-234
• /
• 2013

The purpose of this study is to develop a lighting apparatus of the illuminance and color temperature to maximize the ability of the optimal combination of light sources that can be controlled efficiently control device. Finding people comfortable feeling for indoor lighting that can be used in a variety of color temperature illumination area by combining light sensitivity can be realized. Lighting apparatus for fluorescent lamps with different color temperature of 2000K and 8000K, and by varying the quantity of each of the fluorescent lamps, the illuminance of lighting equipment and color temperature through optical simulations were evaluated. By infrared remote control receiver, divided into 5 types of relaxation, conversation, meeting, hospitality, arts and the lighting environment you want to transfer the PC0 ~ PC4 through the parallel port on the mode selected by the user at the receiving end the DC voltage output. EEFL inverter input DC voltage and the DC input voltage, depending on the level of EEFL dimming value (illuminance and color temperature) lighting environment you want to create change while using a PIR sensor EEFL automatically turn off if people do not have was developed so that the power consumption so you can save.