• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.331-331
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• 2012

With the NAND Flash scaling down, it becomes more and more difficult to follow Moore's law to continue the scaling due to physical limitations. Recently, three-dimensional (3D) flash memories have introduced as an ideal solution for ultra-high-density data storage. In 3D flash memory, as the process reason, we need to use poly-Si TFTs instead of conventional transistors. So, after combining charge trap flash (CTF) structure and poly-Si TFTs, the emerging device SONOS-TFTs has also suffered from some reliability problem such as hot carrier degradation, charge-trapping-induced parasitic capacitance and resistance which both create interface traps. Charge pumping method is a useful tool to investigate the degradation phenomenon related to interface trap creation. However, the curves for charge pumping current in SONOS TFTs were far from ideal, which previously due to the fabrication process or some unknown traps. It needs an optimization and the important geometrical effect should be eliminated. In spite of its importance, it is still not deeply studied. In our work, base-level sweep model was applied in SONOS TFTs, and the nonideal charge pumping current was optimized by adjusting the gate pulse transition time. As a result, after the optimizing, an improved charge pumping current curve is obtained.

• Transactions on Electrical and Electronic Materials
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• v.16 no.4
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• pp.183-186
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• 2015

This research investigates the impact of charge spreading on the data retention of three-dimensional (3D) silicon-oxide-nitride-oxide-silicon (SONOS) flash memory where the charge trapping layer is shared along the cell string. In order to do so, this study conducts an electrical analysis of the planar SONOS test pattern where the silicon nitride charge storage layer is not isolated but extends beyond the gate electrode. Experimental results from the test pattern show larger retention loss in the devices with extended storage layers compared to isolated devices. This retention degradation is thought to be the result of an additional charge spreading through the extended silicon nitride layer along the width of the memory cell, which should be improved for the successful 3-D application of SONOS flash devices.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.2
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• pp.877-880
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• 2005

As DMB, 3D game, Internet and movie is serviced for the recent mobile devices, high resolution display devices beyond VGA become used. Implementation of real-time moving pictures of 30렌 by software programming is difficult because the performance of mobile processors is not so high. The full frame moving picture can be supported by using specific hardware. In this paper, an OLED controller that is consists of flash memory controller and OLED interface is proposed for real-time moving picture on mobile displays. The proposed OLED controller is implemented in FPGA and the performance is evaluated.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.11
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• pp.219-225
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• 2013

Program and erase characteristics of the elliptic gate all around (e-GAA) SONOS cell have been studied as the variation of eccentricity of the channel. An analytic program and erase model for the elliptic GAA SONOS cell is proposed and evaluated. The model shows that the ISPP (incremental-step-pulse programming) property is changed non-linearly as the eccentricity of the e-GAA SONOS cell is increased. It is differently from the well known linear relationship for that of 2D SONOS and even 3D circular SONOS cell with program bias. We can find that the simulation results of ISPP characteristics are in accord with the experimental data.

• Bulletin of the Korean Chemical Society
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• v.30 no.12
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• pp.2973-2978
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• 2009

The decomposition reaction mechanism of $CH_3CF_2O$ radical formed from hydroflurocarbon, $CH_3CHF_2$ (HFC-152a) in the atmosphere has been investigated using ab-initio quantum mechanical methods. The geometries of the reactant, products and transition states involved in the decomposition pathways have been optimized and characterized at DFT-B3LYP and MP2 levels of theories using 6-311++G(d,p) basis set. Calculations have been carried out to observe the effect of basis sets on the optimized geometries of species involved. Single point energy calculations have been performed at QCISD(T) and CCSD(T) level of theories. Out of the two prominent decomposition channels considered viz., C-C bond scission and F-elimination, C-C bond scission is found to be the dominant path involving a barrier height of 12.3 kcal/mol whereas the F-elimination path involves that of a 28.0 kcal/mol. Using transition-state theory, rate constant for the most dominant decomposition pathway viz., C-C bond scission is calculated at 298 K and found to be 1.3 ${\times}$ 10$^4s{-1}$. Transition states are searched on the potential energy surfaces involving both decomposition channels and each of the transition states are characterized. The existence of transition states on the corresponding potential energy surface are ascertained by performing Intrinsic Reaction Coordinate (IRC) calculation.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.67 no.6
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• pp.745-752
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• 2018

ICs(Integrated circuits) for nuclear power plant exposed to radiation environment occur malfunctions and data errors by the TID(Total ionizing dose) effects among radiation-damage phenomenons. In order to protect ICs from the TID effects, this paper proposes a radiation-hardening of the logic circuit(D-latch) which used for the data synchronization and the clock division in the ICs design. The radiation-hardening technology in the logic device(NAND) that constitutes the proposed RH(Radiation-hardened) D-latch is structurally more advantageous than the conventional technologies in that it keeps the device characteristics of the commercial process. Because of this, the unit cell based design of the RH logic device is possible, which makes it easier to design RH ICs, including digital logic circuits, and reduce the time and cost required in RH circuit design. In this paper, we design and modeling the structure of RH D-latch based on commercial $0.35{\mu}m$ CMOS process using Silvaco's TCAD 3D tool. As a result of verifying the radiation characteristics by applying the radiation-damage M&S (Modeling&Simulation) technique, we have confirmed the radiation-damage of the standard D-latch and the RH performance of the proposed D-latch by the TID effects.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.3
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• pp.154-161
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• 2006

This paper describes the new types of ngative differential resistance (NDR) IC applications which use a monolithic quantum-effect device technology based on the RTD/HBT heterostructure design. As a digital IC, a low-power/high-speed MOBILE (MOnostable-BIstable transition Logic Element)-based D-flip flop IC operating in a non-return-to-zero (NRZ) mode is proposed and developed. The fabricated NRZ MOBILE D-flip flop shows high speed operation up to 34 Gb/s which is the highest speed to our knowledge as a MOBILE NRZ D-flip flop, implemented by the RTD/HBT technology. As an analog IC, a 14.75 GHz RTD/HBT differential-mode voltage-controlled oscillator (VCO) with extremely low power consumption and good phase noise characteristics is designed and fabricated. The VCO shows the low dc power consumption of 0.62 mW and good F.O.M of -185 dBc/Hz. Moreover, a high-speed CML-type multi-functional logic, which operates different logic function such as inverter, NAND, NOR, AND and OR in a circuit, is proposed and designed. The operation of the proposed CML-type multi-functional logic gate is simulated up to 30 Gb/s. These results indicate the potential of the RTD based ICs for high speed digital/analog applications.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.118.2-118.2
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• 2016

3D NAND 제조에 있어 high-aspect-ratio etch 공정을 견뎌낼 수 있는 hardmask 소재로서 amorphous carbon layer (ACL) 가 각광받고 있으며 hardmask로서의 특성을 향상시키기 위해 다양한 연구가 진행중에 있다 [1]. 본 연구팀의 기존 연구에서 질소 및 붕소 doping 된 ACL 박막의 etch rate 및 Raman 분석을 통해 박막 특성을 확인한 바 있었으나, 공정 중 arcing이 일어나는 등 의도치 않은 문제로 인해 공정 최적화에 일부 문제가 존재하였다. 본 연구에서는 plasma enhanced chemical vapor deposition (PECVD) 공정을 통해 C6H12 기체 및 doping을 위한 NH3 와 B2H6 두 기체를 이용하여 특성 개선된 ACL을 증착하는 과정에서 발생하는 arcing 및 증착 특성을 규명하고자 진공 내 입자의 수농도를 실시간 측정할 수 있는 particle beam mass spectrometer(PBMS)를 적용, 특정 공정 사건 진단 및 해당 사건에서 발생하는 입자를 분석, 증착된 박막의 Raman spectroscopy 결과와 비교 분석하였다.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2018.06a
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• pp.46-46
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• 2018

메모리 소자의 수요가 데스크톱 컴퓨터의 정체와 모바일 기기의 폭발적인 증가로 NAND flash 메모리의 고집적화로 이어져서 3차원 집적 기술의 고도화가 중요한 요소가 되고 있다. 1 mm 정도의 얇은 웨이퍼 상에 만들어지는 메모리 소자는 실제 두께는 몇 마이크로미터 되지 않는다. 수직방향으로 여러 장의 웨이퍼를 연결하면 폭 방향으로 이미 거의 한계에 도달해있는 크기 축소(shrinking) 기술에 의지 하지 않고서도 메모리 소자의 용량을 증대 시킬 수 있다. CPU, AP등의 논리 연산 소자의 경우에는 발열 문제로 3D stacking 기술의 구현이 쉽지 않지만 메모리 소자의 경우에는 저 전력화를 통해서 실용화가 시작되었다. 스마트폰, 휴대용 보조 저장 매체(USB memory, SSD)등에 수 십 GB의 용량이 보편적인 현재, FEOL, BEOL 기술을 모두 가지고 있는 국내의 반도체 소자 업체들은 자연스럽게 TSV 기술과 이에 필요한 장비의 개발에 관심을 가지게 되었다. 특히 이 중 TSV용 스퍼터링 장치는 transistor의 main contact 공정에 전 세계 시장의 90% 이상을 점유하고 있는 글로벌 업체의 경우에도 완전히 만족스러운 장비를 공급하지는 못하고 있는 상태여서 연구 개발의 적절한 시기이다. 기본 개념은 일반적인 마그네트론 스퍼터링이 중성 입자를 타겟 표면에서 발생시키는데 이를 다시 추가적인 전력 공급으로 전자 - 중성 충돌로 인한 이온화 과정을 추가하고 여기서 발생된 타겟 이온들을 웨이퍼의 표면에 최대한 수직 방향으로 입사시키려는 노력이 핵심이다. 본 발표에서는 고전력 이온화 스퍼터링 시스템의 자기장 해석, 냉각 효율 해석, 멀티 모듈 회전 자석 음극에 대한 동역학적 분석 결과를 발표한다. 그림1에는 이중 회전 모듈에 대한 다물체 동역학 해석을 Adams s/w package로 해석하기 위하여 작성한 모델이고 그림2는 180도 회전한 서브 모듈의 위상이 음극 냉각에 미치는 효과를 CFD-ACE+로 유동 해석한 결과를 나타내고 있다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.82-82
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• 2008

One-dimensional (1D) nanowires have been received much attention due to their potential for applications in various field. Recently some logic applications fabricated on various nanowires, such as ZnO, CdS, Si, are reported. These logic circuits, which consist of two- or three field effect transistors(FETs), are basic components of computation machine such as central process unit (CPU). FETs fabricated on nanowire generally have surrounded shapes of gate structure, which improve the device performance. Highly integrated circuits can also be achieved by fabricating on nano-scaled nanowires. But the numerical and SPICE simulation about the logic circuitry have never been reported and analyses of detailed parameters related to performance, such as channel doping, gate shapes, souce/drain contact and etc., were strongly needed. In our study, NAND and NOT logic circuits were simulated and characterized using 2- and 3-dimensional numerical simulation (SILVACO ATLAS) and built-in spice module(mixed mode).