• Journal of the Korean Society for Precision Engineering
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• v.31 no.10
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• pp.865-871
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• 2014

Paradigm shift to 3-D chip stacking in electronic packaging has induced a lot of integration challenges due to the reduction in wafer thickness and pitch size. This study presents a hybrid bonding technology by self-alignment effect in order to improve the flip chip bonding accuracy with ultra-thin wafer. Optimization of Cu pillar bump formation and evaluation of various factors on self-alignment effect was performed. As a result, highly-improved bonding accuracy of thin wafer with a $50{\mu}m$ of thickness was achieved without solder bridging or bump misalignment by applying reflow process after thermo-compression bonding process. Reflow process caused the inherently-misaligned micro-bump to be aligned due to the interface tension between Si die and solder bump. Control of solder bump volume with respect to the chip dimension was the critical factor for self-alignment effect. This study indicated that bump design for 3D packaging could be tuned for the improvement of micro-bonding quality.

• Journal of Korea Multimedia Society
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• v.24 no.11
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• pp.1472-1480
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• 2021

Image stacking technique is one of the key techniques for complex surface reconstruction. The process includes sample collection, image processing, algorithm editing, surface reconstruction, and finally reaching reliable conclusions. Since this experiment is based on laser scanning confocal microscope to collect the original contour information of the sample, it is necessary to briefly introduce the relevant principle and operation method of laser scanning confocal microscope. After that, the original image is collected and processed, and the data is expanded by interpolation method. Meanwhile, several methods of surface reconstruction are listed. After comparing the advantages and disadvantages of each method, one-dimensional interpolation and volume rendering are finally used to reconstruct the 3D model. The experimental results show that the final 3d surface modeling is more consistent with the appearance information of the original samples. At the same time, the algorithm is simple and easy to understand, strong operability, and can meet the requirements of surface reconstruction of different types of samples.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2012.10a
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• pp.467-468
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• 2012

• Journal of Power Electronics
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• v.19 no.6
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• pp.1449-1457
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• 2019

This paper presents two voltage domain stacking topologies for powering integrated digital loads such as multiprocessors or 3D integrated circuits. Pairs of loads and capacitors are connected in series to form a stack of voltage domains. The voltage is balanced by switching the position of the capacitors in one case and the position of the loads in the other case. This method makes the voltage regulation robust to large differential load power consumption. The first configuration can be named the load stacking topology. The second configuration can be named the capacitor stacking topology. This paper aims at proposing and comparing these two topologies. Models of both topologies and a switching scheme are presented. The behavior, control scheme, losses and overall performance are analyzed and compared theoretically in simulation and experiments. Experimental results show that the capacitor stacking topology has better performance with a 30% voltage ripple reduction.

• Journal of the Microelectronics and Packaging Society
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• v.19 no.1
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• pp.25-32
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• 2012

Package for artificial satellite is to produce mass production for high package with reliability certification as well as develop SDRAM (synchronous dynamic RAM) module which has such as miniaturization, mass storage, and high reliability in space environment. It requires sophisticated technology with chip stacking or package stacking in order to increase up to 4Gbits or more for mass storage with space technology. To make it better, we should secure suitable processes by doing design, manufacture, and debugging. Pin type PCB substrate was then applied to QFP-Pin type 3D memory package fabrication. These results show that the 3D memory package for artificial satellite scheme is a promising candidate for the realization of our own domestic technologies.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.28 no.3
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• pp.281-288
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• 2004

The hybrid composite material (Al/GFRP laminates) are applied to the fuselage and wing in a aircraft. Therefore, Al/GFRP laminates suffer from the cyclic bending moments. This study was to evaluate the effect of fiber stacking angle on the fatigue crack propagation and delamination behavior using the relationship between crack growth rate (da/dN) and stress intensity factor range (ΔK) in Al/GFRP laminates under cyclic bending moment. The variable delamination growth behavior in case of three different type of fiber orientations, i.e., [Al/O$_2$/Al], [Al/+45$_2$/Al] and [Al/90$_2$/Al] at the interface of Al layer and glass fiber layer was measured by ultrasonic C-scan images. As results of this study, It represent that the delamination shape should turns out to have more effective characteristics on the fiber stacking angle. The extension of the delamination zone in case of [Al/+45$_2$/Al] and [Al/90$_2$/Al] were not formed along the fatigue crack profile. The shape of delamination zone depend on fiber stacking angle and the variable type with the delamination contour decreased non-linearly toward the crack tip at the Al layer.

• Journal of the Microelectronics and Packaging Society
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• v.28 no.2
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• pp.1-12
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• 2021

3D printing, which designs product in three dimensions, draws attention as a technology that will lead the future for it dramatically shortens time for production without assembly, no matter how complex the structure is. The paper studies the latest researches of 3D-printed electronics and introduces papers studied electronics components, power supply, circuit interconnection and 3D-printed PCBs' applications. 3D-printed electronics showed possibility to simplify facilities and personalize electric devices by providing one-stop printing process of electronic components, soldering, stacking, and even encapsulation.

• Journal of Surface Science and Engineering
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• v.54 no.5
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• pp.207-212
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• 2021

The mechanical and electrical characteristics can be improved in 3D stacked IC technology which can accomplish the ultra-high integration by stacking more semiconductor chips within the limited package area through the Cu direct bonding method minimizing the performance degradation to the bonding surface to the inorganic compound or the oxide film etc. The surface was treated in a ultrasonic washer using a diamond abrasive to remove other component substances from the prepared cast plate substrate surface. FE-SEM was used to analyze the bonding characteristics of the bonded copper substrates, and the cross section of the bonded Cu conjugates at the sintering junction temperature of 100 ℃, 150 ℃, 200 ℃, 350 ℃ and the pressure of 2303 N/cm² and 3087 N/cm². At 2303 N/cm², the good bonding of copper substrate was confirmed at 350 ℃, and at the increased pressure of 3087 N/cm², the bonding condition of Cu was confirmed at low temperature junction temperature of 200 ℃. However, the recrystallization of Cu particles was observed due to increased pressure of 3087 N/cm² and diffusion of Cu atoms at high temperature of 350 ℃, which can lead to degradation in semiconductor manufacturing.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.3
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• pp.202-209
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• 2014

In this paper, we analyzed the effects by multi-stacking superstrates over the circular-polarized patch antenna. The previous works considered a single-layered superstrate or a superstrate with multiple layers, and did not almost consider the axial ratio at the performance analysis. First, the effect of center frequency shift is analyzed by the variation of air-gap height between patch antenna and superstrate. The center frequency is down-shifted at the smaller air-gap height and has almost the same frequency as patch antenna at the air-gap height of $005{\lambda}_0$. Second, the antenna performance is analyzed by multi-stacking superstrates with the air-gap height of $005{\lambda}_0$. As the number of multi-stacked superstrates increase, antenna gain has a linear increase and axial ratio is exponentially deteriorated. In addition, it has also been observed that the antenna performance has the same trend with the number of multi-stacked superstrates as the thickness of superstrate increases. Finally, we confirmed that it is possible to design the CP patch antenna with the scalable gain and less than 3dB axial ratio by stacking the superstrate.

• Journal of the Microelectronics and Packaging Society
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• v.19 no.3
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• pp.37-41
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• 2012

The wafer level stacking with Cu-to-Cu bonding becomes an important technology for high density DRAM stacking, high performance logic stacking, or heterogeneous chip stacking. Cu CMP becomes one of key processes to be developed for optimized Cu bonding process. For the ultra low-k dielectrics used in the advanced logic applications, Ti barrier has been preferred due to its good compatibility with porous ultra low-K dielectrics. But since Ti is electrochemically reactive to Cu CMP slurries, it leads to a new challenge to Cu CMP. In this study Ti barrier/Cu interconnection structure has been investigated for the wafer level 3D integration. Cu CMP wafers have been fabricated by a damascene process and two types of slurry were compared. The slurry selectivity to $SiO_2$ and Ti and removal rate were measured. The effect of metal line width and metal density were evaluated.