• International Journal of Internet, Broadcasting and Communication
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• 제12권4호
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• pp.55-60
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• 2020

This study aims to apply Arduino and 3D printing technology considered as a key subject in the age of 4th industrial revolution which is a step 1 for customizing and applying the process of production by chemical molding companies producing environment-friendly biodegradable packaging materials to the 3D printing teaching in universities. Step 3 is applied to IoT for Arduino application, and 3D printing technology is also used on the basis of teaching creative integrated human resource. Integration of Arduino with 3D printers is based on the assumption that middle- and high-school students can learn it step by step to higher levels and university students majoring or not majoring in computing science can also have computing skills for solving 3D printing-based problems. For IoT application in this study, the 3D printing technology is applied to the external shape of products for producing an Arduino-based lighting fixture. The applied 3D printing technology is further extended to teaching modeling of producing packaging materials by chemical product molding companies in the age of 4th industrial revolution.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2002년도 춘계 기술심포지움 논문집
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• pp.1-6
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• 2002

It is very important to foresee the main stream of technology development in the future. Packaging related manufacturers in equipment and materials focused their strength on products sharing big portion of world markets. As a result, domestic supply sources for packaging materials and equipment has been increased, but the manufacturer's capital and manpower is so limited to develop high technology machinery and high functional materials. The current status of packaging infrastructures in Korea is reviewed statistically. The hot issues in packaging arena are now in wafer level packaging, 3D packaging, and ultra-thin packaging. In addition, the recent advancement in microelectronics packaging technology is also covered.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.45-46
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• 2006

An ultrawide bandpass filter with sharp rejection and wider stopband is designed and implemented using multilayer ceramic configuration. The proposed filter is composed of a broadside coupled structure and a ring type filter with an embedded stripline stub. The measured results show that the fractional bandwidth and upper stopband of the proposed filter are 106 % and better than -30 dB, respectively. The insertion loss is less than 1 dB, and group delay is less than 0.3 ns in the passband. In addition, ring and broadside coupled gap structures are characterized and compared to the proposed structure.

• 마이크로전자및패키징학회지
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• 제28권2호
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• pp.1-12
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• 2021

3차원 인쇄 기술은 제품의 설계를 3차원으로 하여 조립없이 제품의 생산까지의 시간을 획기적으로 줄이고 복잡한 구조도 구현할 수 있어 미래의 기술로 각광받고 있다. 본 논문은 3차원 인쇄기술을 이용한 전자소자에 대한 최근 연구동향을 알아보면서 구성품, 전원공급장치와 회로에서의 연결과 3차원 인쇄기술 PCB의 응용한 연구논문들을 소개하고 있다. 3차원 인쇄기술로 제작한 전자소자는 원스톱으로 전자소자, 솔더링(soldering), 스태킹(stacking), 회로의 봉지막(encapsulation)까지 제작함으로써 생산설비의 단순화와 전자기기를 개인 맞춤형을 할 수 있는 가능성을 보여주었다.

• 한국재료학회지
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• 제17권7호
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• pp.347-351
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• 2007

Vertical interconnect technology called 3D stacking has been a major focus of the next generation of IC industries. 3D stacked devices in the vertical dimension give several important advantages over conventional two-dimensional scaling. The most eminent advantage is its performance improvement. Vertical device stacking enhances a performance such as inter-die bandwidth improvements, RC delay mitigation and geometrical routing and placement advantages. At present memory stacking options are of great interest to many industries and research institutes. However, these options are more focused on a form factor reduction rather than the high performance improvements. In order to improve a stacked device performance significantly vertical interconnect technology with wafer level stacking needs to be much more progressed with reduction in inter-wafer pitch and increases in the number of stacked layers. Even though 3D wafer level stacking technology offers many opportunities both in the short term and long term, the full performance benefits of 3D wafer level stacking require technological developments beyond simply the wafer stacking technology itself.

• E2M - 전기 전자와 첨단 소재
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• 제22권12호
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• pp.23-29
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• 2009

• 대한전자공학회논문지SD
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• 제43권9호
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• pp.64-68
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• 2006

본 연구에서는 Si bump를 이용해 기판의 기계적, 열적 특성을 개선한 MCM-D 기판공정을 개발하였고, 이를 system-on-package(SOP)-D개념의 system 구현에 적용하고자 하였다. 이 과정에서 밀리미터파 대역에 적용될 수 있는 필터를 설계하고 구현하여 그 특성을 관찰하였다. 두 가지 형태의 필터를 구현하였는데 첫 번째는 공진기간의 커플링을 이용한 구조로서 2층의 금속층과 3층의 유전체(BCB)를 이용하였다. 구현된 필터 특성은 중심주파수 55 GHz에서의 삽입손실이 2.6 dB이고 군지연이 0.06 ns정도로 우수한 특성을 나타내었다. 또한 일반적으로 알려진coupled line 형태의 필터를 구현하였는데 삽입손실이 3 dB, 군지연이 0.1 ns정도의 특성을 나타내었다. 이렇게 내장형 필터를 포함한 MCM-D 기판은 MMIC를 flip-chip 방법으로 실장 할 수 있어서 집적화된 밀리미터파 대역 초소형 system 구현에 적용되어 우수한 특성을 나타낼 것으로 기대된다.

• 마이크로전자및패키징학회지
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• 제22권4호
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• pp.7-14
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• 2015

Research and application of three dimensional packaging technology in electronics have been increasing according to the trend of high density, high capacity and light weight in electronics. In this paper, TSV fabrication and research trend in three dimensional packaging are reported. Low alpha solder bumping which can solve the soft error problem in electronics is also introduced. In detail, this paper includes fabrication of TSV, functional layers deposition, Cu filling in TSV by electroplating using PPR (periodic pulse reverse) and 3 step PPR processes, and low alpha solder bumping on TSV by solder ball. TSV and low alpha solder bumping technologies need more studies and improvements, and the drawbacks of three dimensional packaging can be solved gradually through continuous attentions and researches.

• Journal of Welding and Joining
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• 제31권3호
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• pp.11-16
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• 2013

Through-silicon-via (TSV) is a major technology in microelectronics for three dimensional high density packaging. The 3-dimensional TSV technology is applied to CMOS sensors, MEMS, HB-LED modules, stacked memories, power and analog, SIP and so on which can be employed to car electronics. The copper electroplating is widely used in the TSV filling process. In this paper, the various Cu filling methods using the control of the plating process were described in detail including recent studies. Via filling behavior by each method was also introduced.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 추계학술대회 논문집
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• pp.390-391
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• 2007

LED Packaging 과정 중 Die bond 재료로 Silver epoxy를 사용하여 Packaging 한 후 T3Ster 장비로 열 저항 값(Rth)을 측정하였다. Silver epoxy 의 접착 두께를 조절하여 열 저항 값을 측정하였고, 열전도도 값이 다른 Silver epoxy를 사용하여 열 저항 값을 측정하였다. Silver epoxy 접착 두께가 충분하여 Chip 전면에 고루 분포되었을 경우 그렇지 않은 경우보다 평균 4.8K/W 낮은 13.23K/W의 열 저항 값을 나타내었고, 열전도도가 높은 Silver epoxy 일수록 열전도도가 낮은 재료보다 평균 4.1K/W 낮은 12K/W의 열 저항 값을 나타내었다.