• Title/Summary/Keyword: 3D input device

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RF Energy Harvesting and Charging Circuits for Low Power Mobile Devices

  • Ahn, Chang-Jun;Kamio, Takeshi;Fujisaka, Hisato;Haeiwa, Kazuhisa
    • IEIE Transactions on Smart Processing and Computing
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    • v.3 no.4
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    • pp.221-225
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    • 2014
  • Low power RF devices, such as RFID and Zigbee, are important for ubiquitous sensing. These devices, however, are powered by portable energy sources, such as batteries, which limits their use. To mitigate this problem, this study developed RF energy harvesting with W-CDMA for a low power RF device. Diodes are required with a low turn on voltage because the diode threshold is larger than the received peak voltage of the rectifying antenna (rectenna). Therefore, a Schottky diode HSMS-286 was used. A prototype of RF energy harvesting device showed the maximum gain of 5.8dBi for the W-CDMA signal. The 16 patch antennas were manufactured with a 10 dielectric constant PTFT board. In low power RF devices, the transmitter requires a step-up voltage of 2.5~5V with up to 35 mA. To meet this requirement, the Texas Instruments TPS61220 was used as a low input voltage step-up converter. From the evaluated result, the achievable incident power of the rectenna at 926mV to operate Zigbee can be obtained within a distance of 12m.

5D Light Field Synthesis from a Monocular Video (단안 비디오로부터의 5차원 라이트필드 비디오 합성)

  • Bae, Kyuho;Ivan, Andre;Park, In Kyu
    • Journal of Broadcast Engineering
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    • v.24 no.5
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    • pp.755-764
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    • 2019
  • Currently commercially available light field cameras are difficult to acquire 5D light field video since it can only acquire the still images or high price of the device. In order to solve these problems, we propose a deep learning based method for synthesizing the light field video from monocular video. To solve the problem of obtaining the light field video training data, we use UnrealCV to acquire synthetic light field data by realistic rendering of 3D graphic scene and use it for training. The proposed deep running framework synthesizes the light field video with each sub-aperture image (SAI) of $9{\times}9$ from the input monocular video. The proposed network consists of a network for predicting the appearance flow from the input image converted to the luminance image, and a network for predicting the optical flow between the adjacent light field video frames obtained from the appearance flow.

Implementation of a Window-Masking Method and the Soft-core Processor based TDD Switching Control SoC FPGA System (윈도 마스킹 기법과 Soft-core Processor 기반 TDD 스위칭 제어 SoC 시스템 FPGA 구현)

  • Hee-Jin Yang;Jeung-Sub Lee;Han-Sle Lee
    • The Journal of Korea Institute of Information, Electronics, and Communication Technology
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    • v.17 no.3
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    • pp.166-175
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    • 2024
  • In this paper, the Window-Masking Method and HAT (Hardware Attached Top) CPU SoM (System on Module) are used to improve the performance and reduce the weight of the MANET (Mobile Ad-hoc Network) network synchronization system using time division redundancy. We propose converting it into a RISC-V based soft-core MCU and mounting it on an FPGA, a hardware accelerator. It was also verified through experiment. In terms of performance, by applying the proposed technique, the synchronization acquisition range is from -50dBm to +10dBm to -60dBm to +10dBm, the lowest input level for synchronization is increased by 20% from -50dBm to -60dBm, and the detection delay (Latency) is 220ns. Reduced by 43% to 125ns. In terms of weight reduction, computing resources (48%), size (33%), and weight (27%) were reduced by an average of 36% by replacing with soft-core MCU.

A 12b 130MS/s 108mW $1.8mm^2$ 0.18um CMOS ADC for High-Quality Video Systems (고화질 영상 시스템 응용을 위한 12비트 130MS/s 108mW $1.8mm^2$ 0.18um CMOS A/D 변환기)

  • Han, Jae-Yeol;Kim, Young-Ju;Lee, Seung-Hoon
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.45 no.3
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    • pp.77-85
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    • 2008
  • This work proposes a 12b 130MS/s 108mW $1.8mm^2$ 0.18um CMOS ADC for high-quality video systems such as TFT-LCD displays and digital TVs requiring simultaneously high resolution, low power, and small size at high speed. The proposed ADC optimizes power consumption and chip area at the target resolution and sampling rate based on a three-step pipeline architecture. The input SHA with gate-bootstrapped sampling switches and a properly controlled trans-conductance ratio of two amplifier stages achieves a high gain and phase margin for 12b input accuracy at the Nyquist frequency. A signal-insensitive 3D-fully symmetric layout reduces a capacitor and device mismatch of two MDACs. The proposed supply- and temperature- insensitive current and voltage references are implemented on chip with a small number of transistors. The prototype ADC in a 0.18um 1P6M CMOS technology demonstrates a measured DNL and INL within 0.69LSB and 2.12LSB, respectively. The ADC shows a maximum SNDR of 53dB and 51dB and a maximum SFDR of 68dB and 66dB at 120MS/s and 130MS/s, respectively. The ADC with an active die area of $1.8mm^2$ consumes 108mW at 130MS/s and 1.8V.

Hardware Channel Decoder for Holographic WORM Storage (홀로그래픽 WORM의 하드웨어 채널 디코더)

  • Hwang, Eui-Seok;Yoon, Pil-Sang;Kim, Hak-Sun;Park, Joo-Youn
    • Transactions of the Society of Information Storage Systems
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    • v.1 no.2
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    • pp.155-160
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    • 2005
  • In this paper, the channel decoder promising reliable data retrieving in noisy holographic channel has been developed for holographic WORM(write once read many) system. It covers various DSP(digital signal processing) blocks, such as align mark detector, adaptive channel equalizer, modulation decoder and ECC(error correction code) decoder. The specific schemes of DSP are designed to reduce the effect of noises in holographic WORM(H-WORM) system, particularly in prototype of DAEWOO electronics(DEPROTO). For real time data retrieving, the channel decoder is redesigned for FPGA(field programmable gate array) based hardware, where DSP blocks calculate in parallel sense with memory buffers between blocks and controllers for driving peripherals of FPGA. As an input source of the experiments, MPEG2 TS(transport stream) data was used and recorded to DEPROTO system. During retrieving, the CCD(charge coupled device), capturing device of DEPROTO, detects retrieved images and transmits signals of them to the FPGA of hardware channel decoder. Finally, the output data stream of the channel decoder was transferred to the MPEG decoding board for monitoring video signals. The experimental results showed the error corrected BER(bit error rate) of less than $10^{-9}$, from the raw BER of DEPROTO, about $10^{-3}$. With the developed hardware channel decoder, the real-time video demonstration was possible during the experiments. The operating clock of the FPGA was 60 MHz, of which speed was capable of decoding up to 120 mega channel bits per sec.

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Millimeter-wave Broadband Amplifier integrating Shunt Peaking Technology with Cascode Configuration (Cascode 구조에 Shunt Peaking 기술을 접목시킨 밀리미터파 광대역 Amplifier)

  • Kwon, Hyuk-Ja;An, Dan;Lee, Mun-Kyo;Lee, Sang-Jin;Moon, Sung-Woon;Baek, Tae-Jong;Park, Hyun-Chang;Rhee, Jin-Koo
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.43 no.10 s.352
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    • pp.90-97
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    • 2006
  • We report our research work on the millimeter-wave broadband amplifier integrating the shunt peaking technology with the cascode configuration. The millimeter-wave broadband cascode amplifier on MIMIC technology was designed and fabricated using $0.1{\mu}m\;{\Gamma}-gate$ GaAs PHEMT, CPW, and passive library. The fabricated PHEMT has shown a transconductance of 346.3 mS/mm, a current gain cut off frequency ($f_T$) of 113 GHz, and a maximum oscillation frequency ($f_{max}$) of 180 GHz. To prevent oscillation of designed cascode amplifier, a parallel resistor and capacitor were connected to drain of common-gate device. For expansion of the bandwidth and flatness of the gain, we inserted the short stub into bias circuits and the compensation transmission line between common-source device and common-gate device, and then their lengths were optimized. Also, the input and output stages were designed using the matching method to obtain the broadband characteristic. From the measurement, we could confirm to extend bandwidth and flat gain by integrating the shunt peaking technology with the cascode configuration. The cascode amplifier shows the broadband characteristic from 19 GHz to 53.5 GHz. Also, the average gain of this amplifier is about 6.5 dB over the bandwidth.

A Numerical Study on Natural Convection in A Three-Phase GIS Busbar (3상 GIS Busbar내 자연대류에 대한 수치해석적 연구)

  • Wang, Yangyang;Hahn, Sung-Chin;Kim, Joong-Kyoung;Kang, Sang-Mo
    • 한국전산유체공학회:학술대회논문집
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    • 2008.03b
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    • pp.107-108
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    • 2008
  • The temperature rise of GIS (Gas Insulated Switchgear) busbar system is a vital factor that affects its performance. In this paper, a two-dimensional model is presented by commercial code CFX11 for the evaluation of natural convection in the busbar system. In the model, SF6 (Sulfur Hexafluoride) is used to insulate the high voltage device and improves the heat transfer rate. The power losses of a busbar calculated by the magnetic field analysis are used as the input data to predict the temperature rise by the nature convection analysis. The heat-transfer coefficients on the boundaries are analytically calculated by applying the Nusselt number considering material property and model geometry for the natural convection. The temperatures of the tank and conductors from CFX simulation and the experiment were compared. The results show a good agreement. In the future, we will calculate the 3-D model and try to reduce the temperature by adjusting some dimensional parameters.

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A High Linearity Low Noise Amplifier Using Modified Cascode Structure (높은 선형성을 갖는 새로운 구조의 MMIC 저잡음 증폭기)

  • Park, Seung Pyo;Eu, Kyoung Jun;No, Seung Chang;Lee, Moon-Que
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.27 no.2
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    • pp.220-223
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    • 2016
  • This letter proposes a low noise amplifier which has low noise figure and high linearity simultaneously using a cascode structure with an additional transistor. The proposed structure minimizes the noise source by using optimizing transistor sizes and also improves linearity from the current bleeding technique. The device was fabricated in a $0.5{\mu}m$ GaAs pHEMT process and has noise figure of 1.1 dB, a voltage gain of 15.0 dB, an $OIP_3$ of 30.8 dBm and an input/output return loss of 11.6 dB/10.4 dB from 1.8 to 2.6 GHz.

A 5Watt Power Amplifier Module Using Gallium Nitride Device (질화갈륨소자를 이용한 5Watt급 전력증폭기 모듈)

  • Park, Chun-Seon;Han, Sang-Min;Lim, Jong-Sik;Ahn, Dal;An, Chong-Chul;Park, Ung-Hee
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.9 no.5
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    • pp.1193-1200
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    • 2008
  • This paper describes a developed 5Watt power amplifier module fer mobile communication system using Gallium Nitride (GaN) devices. Three amplification stages such as pre-amplifier, driver amplifier, and power amplifier have been fabricated and measured separately in advance for incorporating the total power amplifier module and estimating the performances. In addition, a defected ground structure is combined with the output stage of the power amplifier module for improving harmonic rejection and adjacent channel power (ACP) characteristics. The measured performances of the GaN power amplifier module include 58dB,min of gain, 37dBm,min of output power, 50dBc,min of harmonic rejection, 35dBc,min of IMD3 for 2-tone input, and 35dBc,min of ACP at 2.1GHz frequency band.

Study on Virtual Reality (VR) Operating System Prototype (가상환경(VR) 운영체제 프로토타입 연구)

  • Kim, Eunsol;Kim, Jiyeon;Yoo, Eunjin;Park, Taejung
    • Journal of Broadcast Engineering
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    • v.22 no.1
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    • pp.87-94
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    • 2017
  • This paper presents a prototype for virtual reality operating system (VR OS) concept with head mount display (HMD) and hand gesture recognition technology based on game engine (Unity3D). We have designed and implemented simple multitasking thread mechanism constructed on the realtime environment provided by Unity3D game engine. Our virtual reality operating system receives user input from the hand gesture recognition device (Leap Motion) to simulate mouse and keyboard and provides output via head mount display (Oculus Rift DK2). As a result, our system provides users with more broad and immersive work environment by implementing 360 degree work space.