• Journal of IKEEE
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• v.25 no.4
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• pp.774-777
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• 2021

In this paper, we analyzed the gate controllability of 3D NAND Flash Memory with Charge Trap Flash using Ferroelectric (CTF-F) structure. HfO₂, a ferroelectric material, has a high-k characteristic besides polarization. Due to these characteristics, gate controllability is increased in CTF-F structure and on/off current characteristics are improved in Bit Line(BL). As a result of the simulation, in the CTF-F structure, the channel length of String Select Line(SSL) and Ground Select Line(GSL) was 100 nm, which was reduced by 33% compared to the conventional CTF structure, but almost the same off-current characteristics were confirmed. In addition, it was confirmed that the inversion layer was formed stronger in the channel during the program operation, and the current through the BL was increased by about 2 times.

• Journal of IKEEE
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• v.28 no.1
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• pp.110-115
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• 2024

This paper analyzed the V_th (Threshold Voltage) variations in 3D NAND Flash memory with tapered O/N/O (Oxide/Nitride/Oxide) structure and O/N/F (Oxide/Nitride/Ferroelectric) structure, where the blocking oxide is replaced by ferroelectric material. With a tapering angle of 0°, the O/N/F structure exhibits lower resistance compared to the O/N/O structure, resulting in reduced V_th variations in both the upper and lower regions of the WL (Word Line). Tapered 3D NAND Flash memory shows a decrease in channel area and an increase in channel resistance as it moves from the upper to the lower WL. Consequently, as the tapering angle increases, the V_th decreases in the upper WL and increases in the lower WL. The tapered O/N/F structure, influenced by V_fe proportional to the channel radius, leads to a greater reduction in V_th in the upper WL compared to the O/N/O structure. Additionally, the lower WL in the O/N/F structure experiences a greater increase in V_th compared to the O/N/O structure, resulting in larger V_th variations with increasing tapering angles.

• Journal of IKEEE
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• v.26 no.2
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• pp.329-332
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• 2022

In this paper, retention characteristics of lateral charge migration according to parameters of 3D NAND flash memory to which ferroelectric (HfO₂) structure is applied and ∆V_th were analyzed. The larger the P_s, the greater maximum polarization possible in ferroelectric during Programming. Therefore, the initial V_th increases by about 1.04V difference at P_s 70µC/cm² than at P_s 25µC/cm². Also, electrons trapped after the Program operation causes lateral charge migration over time. Since ferroelectric maintains polarization without applying voltage to the gate after Programming, regardless of P_s value, polarization increases as P_r increases and the ∆V_th due to lateral charge migration becomes smaller by about 1.54V difference at P_r 50µC/cm² than P_r 5µC/cm².

• Journal of IKEEE
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• v.27 no.4
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• pp.399-404
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• 2023

In this paper, we analyzed the current path in the O/N/O (Oxide/Nitride/Oxide) structure of 3D NAND Flash memory and in the O/N/F (Oxide/Nitride/Ferroelectric) structure where the blocking oxide is replaced by a ferroelectric. In the O/N/O structure, when V_read is applied, a current path is formed on the backside of the channel due to the E-fields of neighboring cells. In contrast, the O/N/F structure exhibits a current path formed on the front side due to the polarization of the ferroelectric material, causing electrons to move toward the channel front. Additionally, we performed an examination of device characteristics considering channel thickness and channel length. The analysis results showed that the front electron current density in the O/N/F structure increased by 2.8 times compared to the O/N/O structure, and the front electron current density ratio of the O/N/F structure was 17.7% higher. Therefore, the front current path is formed more effectively in the O/N/F structure than in the O/N/O structure.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.35 no.3
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• pp.246-254
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• 2022

Localized heat can be generated using electrically conductive word-lines built into a 3D NAND flash memory string. The heat anneals the gate dielectric layer and improves the endurance and retention characteristics of memory cells. However, even though the electro-thermal annealing can improve the memory operation, studies to investigate material failures resulting from electro-thermal stress have not been reported yet. In this context, this paper investigated how applying electro-thermal annealing of 3D NAND affected mechanical stability. Hot-spots, which are expected to be mechanically damaged during the electro-thermal annealing, can be determined based on understanding material characteristics such as thermal expansion, thermal conductivity, and electrical conductivity. Finally, several guidelines for improving mechanical stability are provided in terms of bias configuration as well as alternative materials.

• Proceedings of the Korean Society of Computer Information Conference
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• 2021.07a
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• pp.1-2
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• 2021

3D NAND 플래시 메모리는 플래너(2D) NAND 셀을 적층하는 방식으로 단위 면적당 고용량을 제공한다. 하지만 적층 공정의 특성상 각 레이어별 또는 셀 위치에 따라 오류 발생 빈도가 달라질 수 있는 문제가 있다. 이와 같은 현상은 플래시 메모리의 쓰기/지우기(P/E) 횟수가 증가할 수록 두드러진다. SSD와 같은 대부분의 플래시 기반 저장장치는 오류 교정을 위하여 ECC를 사용한다. 이 방법은 모든 플래시 메모리 페이지에 대하여 고정된 보호 강도를 제공하므로 물리적 위치에 따라 에러 발생률이 각기 다르게 나타나는 3D NAND 플래시 메모리에서는 한계를 보인다. 따라서 본 논문에서는 오류 발생률 차이를 보이는 페이지와 레이어를 분류하여 각 영역별로 차별화된 보호강도를 적용한다. 우리는 페이지와 레이어별로 오류 발생률이 현저하게 달라지는 3K P/E 사이클에서 측정된 오류율을 바탕으로 페이지와 레이어를 분류하고 오류에 취약한 영역에 대해서는 패리티 데이터를 추가하여 차별화된 보호 강도를 제공한다. 오류 발생 횟수에 따른 영역 구분을 위하여 K-Means 머신러닝 알고리즘을 사용한다. 우리는 이와 같은 차별화된 보호정책이 3D NAND 플래시 메모리의 신뢰성과 수명향상에 기여할 수 있는 가능성을 보인다.

• Proceedings of the Korean Vacuum Society Conference
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• 2015.08a
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• pp.92.2-92.2
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• 2015

Negative-AND (NAND) flash의 대용량 및 소형화로 인해 10 nm급 공정을 도입한 128 Gb NAND flash가 개발된 이래, 공정이 미세화되면서 셀이 작이지고 간격이 좁아지게 되었다. 이로 인해 전자가 누설되는 간섭현상이 심화되게 된다. 이러한 문제를 해결하기 위해 기존 NAND의 평면 구조를 수직으로 적층하는 3D NAND 기술이 개발되었으며 차세대 소자를 위한 필수 기술로 각광받고 있다. 3D NAND에서 channel hole etching시 고 선택 비의 중요도가 증가하여 증착막 보호 역할을 하는 hardmask의 두께가 증가하게 되었으며 기존 하드마스크 대비 내식각성이 2배 이상 향상된 hard material 개발이 필요한 실정이다. 본 연구에서는 dopant에 따른 amorphous carbon layer (ACL)의 etch rate의 변화량을 Raman spectroscopy등의 측정장비를 이용하여 비교분석 하였다. dopant의 각각 유량별에 대한 etch rate 변화의 영향성을 비교하였다. dopant의 유량에 따라 etch rate이 변화하는 것을 관찰할 수 있었으며, 2000 sccm 이후에는 etch rate이 급격히 감소하는 경향을 보였다. Raman 측정결과, etch rate의 감소에 따라 G-peak의 red shift가 발생하였으며 두 peak 간의 차이 값이 etch rate의 변화율과 유사한 경향을 보이는 것을 확인하였다.

• Journal of the Semiconductor & Display Technology
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• v.18 no.4
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• pp.138-142
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• 2019

As the NAND flash memory goes to 3D vertical Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) structure, the lateral charge migration can be critical in the reliability performance. Even more, with miniaturization of flash memory cell device, just a little movement of trapped charge can cause reliability problems. In this paper, we propose a method of predicting the trapped charge profile in the retention mode. Charge diffusivity in the charge trapping layer (Si₃N₄) was extracted experimentally, and the effect on the trapped charge profile was demonstrated by the simulation and experiment.

• The KIPS Transactions:PartD
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• v.14D no.7
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• pp.719-726
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• 2007

Recently, NAND flash memory has been used for a storage device in various mobile computing devices such as MP3 players, mobile phones and laptops because of its shock-resistant, low-power consumption, and none-volatile properties. However, due to the very distinct characteristics of flash memory, disk based systems and applications may result in severe performance degradation when directly adopting them on flash memory storage systems. Especially, when a B-tree is constructed, intensive overwrite operations may be caused by record inserting, deleting, and its reorganizing, This could result in severe performance degradation on NAND flash memory. In this paper, we propose an efficient buffer management scheme, called IBSF, which eliminates redundant index units in the index buffer and then delays the time that the index buffer is filled up. Consequently, IBSF significantly reduces the number of write operations to a flash memory when constructing a B-tree. We also show that IBSF yields a better performance on a flash memory by comparing it to the related technique called BFTL through various experiments.

• The Magazine of the IEIE
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• v.42 no.7
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• pp.26-38
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• 2015

고집적화를 위한 Floating Gate NAND 개발과정에서 몇 차례 기술적 한계상황에 직면하였었지만, Air-Gap, Double patterning, Multi-level Cell, Error Correction Code과 같은 breakthrough idea 을 활용하여 1Xnm까지 성공적인 scale-down 을 하였고 10nm 까지도 바라보고 있지만, 10nm 미만으로는 적절한 방안을 찾지 못한 상황입니다. CTD 의 3D NAND Flash는 Aspect Ratio, Poly channel의 intrinsic 특성, Data 보존 능력 등 해결 해야 할 issue 들이 남아 있지만, F.G Flash 의 지난 20년간 Lesson-learn 과 Band engineering, Channel Si, PUC 의 요소기술 개발 및 System algorithm 개발, QLC 개발 등을 통하여 F.G Flash를 넘어 지속적인 Cost-down 이 가능할 것입니다.