• KIPS Transactions on Computer and Communication Systems
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• v.11 no.1
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• pp.1-8
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• 2022

RISC-V is an open-source instruction set architecture which has a simple base structure and can be extensible depending on the purpose. In this paper, we designed a small and low-power 32-bit RISC-V processor to establish the base for research on RISC-V embedded systems. We designed a 2-stage pipelined processor which supports RISC-V base integer instruction set except for FENCE and EBREAK instructions. The processor also supports privileged ISA for trap handling. It used 1895 LUTs and 1195 flip-flops, and consumed 0.001W on Xilinx Zynq-7000 FPGA when synthesized using Vivado Design Suite. GPIO, UART, and timer peripherals are additionally used to compose the system. We verified the operation of the processor on FPGA with FreeRTOS at 16MHz. We used Dhrystone and Coremark benchmarks to measure the performance of the processor. This study aims to provide a low-power, high-efficiency microprocessor for future extension.

• Proceedings of the IEEK Conference
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• 2003.07d
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• pp.1395-1398
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• 2003

This paper presents a 32-bit RISC Micro-Controller which is useful in the dedicated DSP and communication areas. The designed processor has 5 stages pipeline architecture, and 28 instructions. This RISC Micro-Controller consist of 22,100 gates and has 5.95 ns data arrival time, and 437 ㎽ total dynamic power. The RISC Micro-Controller is a IP (Intellectual property) Core module which can implement a number of protocols by and is applicable to DSP and data communication.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1169-1172
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• 1998

We designed an ALU(Airthmetic Logic Unit) with BIST(Built-In Self Test), which is suitable for 32-bit DSP RISC processors. We minimized the area of this ALU by allowing different operations to share several hardware blocks. Moreover, we applied DFT(Design for Testability) to ALU and offered Bist(Built-In Self-Test) function. BIST is composed of pattern generation and response analysis. We used the reseeding method and testability design for the high fault coverage. These techniques reduce the test length. Chip's reliability is improved by testing and the cost of testing system can be reduced.

• 제어로봇시스템학회:학술대회논문집
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• 1989.10a
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• pp.239-243
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• 1989

This paper represents the control software development for Direct Drive Arm Robot with the WHILE language composed the 68000 assembly language and high level language modula-2. Direct Drive Ann Robot needs the control program which is fast step and exactly position moving because Direct Drive Arm Robt depends on accuracy. We found that the self-tuning algorithm for this robot control is very good for the real time control and the floating point operation using the 32 bit CPU(MC 68020) controller.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.416-420
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• 1999

This paper describes a 32-bit RISC processor, which has instruction level compatibility with the ARM7 microprocessor. The processor is fully synthesizable, and its performance is evaluated based on 0.35-${\mu}{\textrm}{m}$ CMOS library. This paper focuses on the implementation of the processor and the reliable verification strategy ensuring the complete instruction level compatibility. The processor has successfully verified using a FPGA chip.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.9
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• pp.55-61
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• 2002

Using the carry-select adder scheme, an adder with small number of stages can be operated as fast as an adder with large number of stages. In this paper, a 4-block 5-stage 32-bit pipelined carry-select adder is designed and implemented. The proposed adder operates as fast as a conventional 16-stage 32-bit pipelined adder while the number of registers required is nearly same as a conventional 4-stage pipelined adder. This adder is operated at 1.67GHz clock frequency in a standard 0.25um CMOS technology with 2.5 V supply voltage.

• Journal of the Semiconductor & Display Technology
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• v.21 no.4
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• pp.27-32
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• 2022

RISC-V is an open instruction set architecture (ISA) developed in 2010 at UC Berkeley, and active research is being conducted as a processor to compete with ARM. In this paper, we propose an SoC system including an RV32I ISA-based 32-bit 5-stage pipeline processor and AHB bus master. The proposed RISC-V processor supports 37 instructions, excluding FENCE, ECALL, and EBREAK instructions, out of a total of 40 instructions based on RV32I ISA. In addition, the RISC-V processor can be connected to peripheral devices such as BRAM, UART, and TIMER using the AHB-lite bus protocol through the proposed AHB bus master. The proposed SoC system was implemented in Arty A7-35T FPGA with 1,959 LUTs and 1,982 flip-flops. Furthermore, the proposed hardware has a maximum operating frequency of 50 MHz. In the Dhrystone benchmark, the proposed processor performance was confirmed to be 0.48 DMIPS.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.10
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• pp.1-6
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• 2007

Wireless Self-Powered Temperature Sensor for UHF Sensor Tags which are basic device for construction of ubiquitous sensor network is proposed. The key parameters of the target specification are resolution of $0.1\;^{\circ}C$ per output bit, below 1.5 V of operating voltage and below 5 uW of power consumption during sensing operation. Temperature sensor circuit consists of PTAT current generator, band gap reference circuit generating both reference voltage and current, Sigma-Delta Converter, and Digital Counter. Simulated maximum resolution was $0.23\;^{\circ}C/bit$ in 11-bit output. The proposed temperature sensor was fabricated by using a 0.25 m CMOS process. The chip area is $0.32\;{\times}\;0.22\;mm$ and the operating frequency is 2 MHz. Measured resolution from fabricated temperature sensor was $4\;^{\circ}C/bit$ in 8-bit output for the temperature range from $10^{\circ}C$ to $80^{\circ}C$.

• Journal of The Institute of Information and Telecommunication Facilities Engineering
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• v.2 no.2
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• pp.32-35
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• 2003

This paper presents a simple method to show that the committed bit based on pseudo-random sequence can be predicted with a probability very close to.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.11
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• pp.123-130
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• 2004

This paper describes a multiplier architecture optimized for 32 bit RISC processor with 3-stage pipeline. The multiplier of ARM7, the target processor, is variably carried out on the execution stage of pipeline within 7 cycles. The included multiplier employs a modified Booth's algerian to produce 64 bit multiplication and addition product and it has 6 separate instructions. We analyzed several multiplication algorithm such as radix4-32${\times}$8, radix4-32${\times}$16 and radix8-32${\times}$32 to decide which multiplication architecture is most fit for a typical architecture of ARM7. VLSI area, cycle delay time and execution cycle number is the index of an efficient design and the final multiplier was designed on these indexes. To verify the operation of embedded multiplier, it was simulated with various audio algorithms.