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Design and Evaluation of 32-Bit RISC-V Processor Using FPGA

FPGA를 이용한 32-Bit RISC-V 프로세서 설계 및 평가

  • Received : 2021.09.28
  • Accepted : 2021.11.22
  • Published : 2022.01.31

Abstract

RISC-V is an open-source instruction set architecture which has a simple base structure and can be extensible depending on the purpose. In this paper, we designed a small and low-power 32-bit RISC-V processor to establish the base for research on RISC-V embedded systems. We designed a 2-stage pipelined processor which supports RISC-V base integer instruction set except for FENCE and EBREAK instructions. The processor also supports privileged ISA for trap handling. It used 1895 LUTs and 1195 flip-flops, and consumed 0.001W on Xilinx Zynq-7000 FPGA when synthesized using Vivado Design Suite. GPIO, UART, and timer peripherals are additionally used to compose the system. We verified the operation of the processor on FPGA with FreeRTOS at 16MHz. We used Dhrystone and Coremark benchmarks to measure the performance of the processor. This study aims to provide a low-power, high-efficiency microprocessor for future extension.

RISC-V는 오픈 소스 명령어 집합 구조로, 간단한 기본 구조를 가지며 목적에 따라 명령어 집합을 유연하게 확장할 수 있다. 본 논문에서는 소형, 저전력 32-bit RISC-V 프로세서를 설계하여 RISC-V 임베디드 시스템 연구를 위한 기반을 마련하고자 하였다. 설계한 프로세서는 2단계 파이프라인으로 구성하였고, RISC-V ISA 중 FENCE, EBREAK 명령어를 제외한 32-bit 정수형 ISA 및 인터럽트 처리를 위한 특권 ISA를 지원한다. Vivado Design Suite를 이용하여 합성한 결과 Xilinx Zynq-7000 FPGA에서 1895개의 LUT 및 1195개의 플립플롭을 사용하였고, 0.001W의 전력을 소모하였다. 이를 GPIO, UART, 타이머와 함께 시스템을 구성하여 합성하였고, FPGA 상에서 FreeRTOS를 포팅하여 16MHz에서의 동작을 검증하였다. Dhrystone, Coremark 벤치마크를 통해 성능을 측정하여 목적에 따라 확장 가능한 저전력 고효율 프로세서임을 보였다.

Keywords

Acknowledgement

본 연구는 삼성전자의 지원(과제번호IO210204-08384-02)을 받아 수행된 결과임. 이 성과는 정부(과학기술정보통신부)의 재원으로 한국연구재단의 지원을 받아 수행된 연구임(NRF-2019R1A2C1088390).

References

  1. A. Waterman, K. Asanovi, and RISC-V Foundation, "The RISC-V instruction set manual, Volume I: User-Level ISA, document version 20191213", 2019.
  2. A. Waterman, K. Asanovi, and RISC-V Foundation, "The RISC-V instruction set manual, Volume II: Privileged architecture, document version 20190608-Priv-MSU-Ratified", 2019.
  3. Asanovic, Krste, and David A. Patterson, "Instruction sets should be free: The case for risc-v," EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2014-146, 2014.
  4. C. Chen, et al., "Xuantie-910: A commercial multi-core 12-stage pipeline out-of-order 64-bit high performance RISC-V processor with vector extension: Industrial product," 2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture (ISCA), pp.52-64, 2020.
  5. Western Digital, "RISC-V SweRV EH2 Programmer's Reference Manual Revision 1.4" [Internet], https://github.com/chipsalliance/Cores-SweRV-EH2, 2021.
  6. M. Gautschi, et al., "Near-threshold RISC-V core with DSP extensions for scalable IoT endpoint devices," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol.25. No.10, pp.2700-2713, 2017. https://doi.org/10.1109/TVLSI.2017.2654506
  7. A. De, A. Basu, S. Ghosh, and T. Jaeger, "FIXER: Flow integrity extensions for embedded RISC-V," 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), IEEE, 2019.
  8. J. J. Lee, J. U. Park, M. J. Kim, and H. W. Kim, "Efficient ARIA cryptographic extension to a RISC-V processor," Journal of The Korea Institute of Information Security & Cryptology, Vol.31, No.3, pp.309-322, 2021. https://doi.org/10.13089/JKIISC.2021.31.3.309
  9. Y. K. Kwak, Y. B. Kim, and S. C. Seo, "Benchmarking Korean Block Ciphers on 32-Bit RISC-V Processor," Journal of The Korea Institute of Information Security & Cryptology, Vol.31, No.3, pp.331-340, 2021. https://doi.org/10.13089/JKIISC.2021.31.3.331
  10. PULPissimo Platform [Internet], https://github.com/pulpplatform/pulpissimo
  11. FreeRTOSTM [Internet], https://www.freertos.org
  12. R. P. Weicker, "Dhrystone: A synthetic systems programming benchmark," Communications of the ACM, Vol.27, No.10, pp.1013-1030, 1984. https://doi.org/10.1145/358274.358283
  13. Coremark® [Internet], https://www.eembc.org/coremark
  14. P. Davide Schiavone et al., "Slow and steady wins the race? A comparison of ultra-low-power RISC-V cores for Internet-of-Things applications," 2017 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), pp.1-8, 2017.
  15. A. Pullini, D. Rossi, I. Loi, G. Tagliavini, and L. Benini, "Mr.Wolf: An energy-precision scalable parallel ultra low power SoC for IoT edge processing," IEEE Journal of Solid-State Circuits, Vol.54, No.7, pp.1970-1981, 2019. https://doi.org/10.1109/jssc.2019.2912307
  16. F. Zaruba and L. Benini, "The cost of application-class processing: Energy and Performance Analysis of a Linux-Ready 1.7-GHz 64-Bit RISC-V Core in 22-nm FDSOI Technology," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol.27, No.11, pp.2629-2640, 2019. https://doi.org/10.1109/tvlsi.2019.2926114
  17. K. Asanovic, et al., "The rocket chip generator," EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS-2016-17, 2016.
  18. Celio, Christopher, David Patterson, and Krste Asanovic, "The Berkeley Out-of-Order Machine (BOOM) Design Specification," University of California, Berkeley, 2016.
  19. PicoRV32 [Internet], https://github.com/cliffordwolf/picorv32
  20. J. Huan, H. Li, F. Wu, and W. Cao, "Design of water quality monitoring system for aquaculture ponds based on NB-IoT," Aquacultural Engineering, Vol.90. No.102088, 2020. https://doi.org/10.1016/j.aquaeng.2020.102088
  21. R. Senthilkumar, P. Venkatakrishnan, and N. Balaji, "Intelligent based novel embedded system based IoT enabled air pollution monitoring system," Microprocessors and Microsystems, Vol.77. No.103172, 2020. https://doi.org/10.1016/j.micpro.2020.103172
  22. M. S. Farooq, S. Riaz, A. Abid, K. Abid, and M. A. Naeem, "A survey on the role of IoT in agriculture for the implementation of smart farming," IEEE Access, Vol.7. pp.156237-156271, 2019. https://doi.org/10.1109/access.2019.2949703
  23. Arm Limited "Arm Cortex-M Processor Comparison Table" 2020 [Internet], https://developer.arm.com/documentation/102787/0100/.
  24. GCC, the GNU Compiler Collection [Internet], https://gcc.gnu.org/onlinedocs/gcc/Optimize-Options.html