• Journal of the Semiconductor & Display Technology
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• v.2 no.1
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• pp.15-19
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• 2003

Spin etcher can process frontside and backside on the wafer, which is used for etching, stripping, cleaning and wafer reclamation. A new generation of spin etchers has been designed to meet 300mm wafer processing. The larger header and higher spin speed make vibration problem a severe problem in developing equipments. This study shows schematic process of solving practical vibration problems, where it is required to analyze the principal ca uses of vibration problem and find out the method of vibration reduction in spin etcher. The vibration under normal operation is measured in time domain and is analyzed in frequency domain. And modal parameters are obtained through modal test. Using the modal parameters from experiments, the model of finite element method is formulated. From diagnosis using many measurements and analyses, it can be shown that main cause of vibration is unbalance of head.

• Proceedings of the KSME Conference
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• 2008.11b
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• pp.2369-2374
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• 2008

In the precision hot plate for wafer processing, the temperature uniformity of upper plate surface is one of the key factors affecting the quality of wafers. Precision hot plates require temperature variations less than ${\pm}1.5%$ during heating to $120^{\circ}C$. In this study, we have manufactured the flat plate heat pipe hot chuck of circle type(300mm) and investigated the operating characteristics of flat plate heat pipe hot chuck experimentally. Various liquids(aceton, FC-40, water) were used as the working fluid and charging ratio was changed($14{\sim}36\;vol.%$). Several cases were tested to improve temperature uniformity. Major working fluid to be investigated was water. Using water, various parameters such as charging ratio, wafer operation on-off time, different working fluids. In case of water, the temperature uniformity was ${\pm}1.5%$, response time of wafer were investigated.

• Journal of the Korean Society for Precision Engineering
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• v.19 no.8
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• pp.180-186
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• 2002

Hot Plate is the major unit that it used to remove damp of wafer surface, to strength adhesion of photoresist (PR) and to bake coated PR in FAB process of semiconductor. The badness of Hot Plate (HP) has directly influence upon the performance of wafer, it is necessary to guarantee the performance of HP. In this study, a reliability evaluation system has been designed and developed, which is to measure and to estimate thermal uniformity and flatness of HP in range of temperature 0~$250^\circC$. This system has included the techniques which measures and analyzes thermal uniformity using infrared thermal vision, and which compensates measuring error of flatness using laser displacement sensor For measuring flatness, a measurement stage of 3 axes are developed which adapts the precision encoder. The allowable error of this system in respect of thermal uniformity is less $than\pm0.1^\circC$ and in respect of flatness is less $than\pm$1mm . It is expected that the developed system can measure from $\Phi200mm\;(wafer 8＂)\;to\;\Phi300mm$ (wafer 12＂) and also can be used in performance test of the Cool Plate and industrial heater, etc.

• Journal of Korea Foundry Society
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• v.33 no.2
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• pp.69-74
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• 2013

Silicon (Si) wafer was grown by using direct growth from Si melt and contaminations of wafer during the process were investigated. In our process, BN was coated inside of all graphite parts including crucible in system to prevent carbon contamination. In addition, coated BN layer enhance the wettability, which ensures the favorable shape of grown wafer by proper flow of Si melt in casting mold. As a result, polycrystalline silicon wafer with dimension of $156{\times}156$ mm and thickness of $300{\pm}20$ um was successively obtained. There were, however, severe contaminations such as BN and SiC on surface of the as-grown wafer. While BN powders were easily removed by brushing surface, SiC could not be eliminated. As a result of BN analysis, C source for SiC was from binder contained in BN slurry. Therefore, to eliminate those C sources, additional flushing process was carried out before Si was melted. By adding 3-times flushing processes, SiC was not detected on the surface of as-grown Si wafer. Polycrystalline Si wafer directly grown from Si melt in this study can be applied for the cost-effective Si solar cells.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.27 no.3
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• pp.137-140
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• 2014

With the recent advent of through silicon via (TSV) technology, wafer level-TSV interconnection become feasible in high volume manufacturing. To increase the manufacturing productivity, it is required to develop equipment for backside passivation layer deposition for TSV wafer bonding process with high deposition rate and low film stress. In this research, we investigated the relationship between process parameters and the induced wafer stress of PECVD silicon nitride film on 300 mm wafers employing statistical and artificial intelligence modeling. We found that the film stress increases with increased RF power, but the pressure has inversely proportional to the stress. It is also observed that no significant stress change is observed when the gas flow rate is low.

• Journal of the Korean institute of surface engineering
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• v.32 no.3
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• pp.239-243
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• 1999

At Present, 200mm wafer technology is being applied for commercial fabrications of 64, 128, and 256 M DRAM devices, and 300mm technology will be evolved for 1G DRAM devices in the early 21th century, recognizing limitations of several process technologies. In particular recognition has been realized in harmful effects of surface contamination of trace metals introduced during devicing processes. Such a guide line for surface metal contamination has been proposed as 1E9 and 1E10 atoms/$\textrm{cm}^2$ of individual metal contamination for wafering and devicing of 1G DRAM, respectively, and so its measurement limit should be at least 1E8 atoms/$\textrm{cm}^2$. The detection limit of present measurement systems is 2E9 atoms/$\textrm{cm}^2$ obtainable with TRXFA(Total Reflection X-Ray Fluorescence Analysis). TRXFA is nondestructive and the simplest in terms of operation, and it maps the whole wafer surfaces but needs detection improvement. X-Ray intensity produced with synchrotron accelerator is much higher than that of conventional X-ray sources by order of 4-5 magnitudes. Hence theoretically its reactivity with silicon surfaces is expected to be much higher than the conventional one, realizing improvement of detection limit. X-ray produced with synchrotron accelerator is illuminated at a very low angle with silicon wafer surfaces such as 0.1 degree and reflects totally. Hence informations only from surface can be collected and utilized without overlapping with bulk informations. This study shows the total reflection phenomenon and quantitative improvement of detection limit for metallic contamination. It is confirmed that synchrotron X-ray can be a very promising alternative for realizing improvement of detection limit for the next generation devices.

• Journal of the Microelectronics and Packaging Society
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• v.12 no.3 s.36
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• pp.197-205
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• 2005

Development of the packaging is one of the critical issues for commercialization of the RF-MEMS devices. RF MEMS package should be designed to have small size, hermetic protection, good RF performance and high reliability. In addition, packaging should be conducted at sufficiently low temperature. In this paper, a low temperature hermetic wafer level packaging scheme for the RF-MEMS devices is presented. For hermetic sealing, Au-Sn eutectic bonding technology at the temperature below $300{\times}C$ is used. Au-Sn multilayer metallization with a square loop of $70{\mu}m$ in width is performed. The electrical feed-through is achieved by the vertical through-hole via filled with electroplated Cu. The size of the MEMS Package is $1mm\times1mm\times700{\mu}m$. By applying $O_2$ plasma ashing and fabrication process optimization, we can achieve the void-free structure within the bonding interface as well as via hole. The shear strength and hermeticity of the package satisfy the requirements of MIL-STD-883F. Any organic gases or contamination are not observed inside the package. The total insertion loss for the packaging is 0.075 dB at 2 GHz. Furthermore, the robustness of the package is demonstrated by observing no performance degradation and physical damage of the package after several reliability tests.

• Journal of Korean Society for Quality Management
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• v.45 no.2
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• pp.293-306
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• 2017

Purpose: In this study, an optimal design level of influencing factors on semiconductor polishing process was determined to minimize flexion of both sides on wafers. Methods: First, significant interactions are determined by the stepwise regression method. ANOVA analysis on SN ratio and mean of dependent variable are performed to draw mean adjustment factors. In addition, the optimal levels of mean adjustment factors are decided by comparing means of each level of mean adjustment factors. Results: As a result of ANOVA, a mean adjustment factor was determined as a width of formed flexion on the plate. The mean of the difference has the nearest to 0 in the case when the width of formed flexion has level 2 (4mm). Conclusion: Optimal design levels of semiconductor polishing process are determined as follows; (i) load applied to the wafer carrier has a level 1 (3psi), (ii) load applied to the wafer has a level 1(3psi), (iii) the amount of slurry supplied during polishing has a level 3 (300 co/min), (iv) the width of formed flexion on the plate has level 2 (4mm).

• Current Applied Physics
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• v.18 no.11
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• pp.1436-1440
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• 2018

SiN and SiCN film production using plasma-enhanced atomic layer deposition (PE-ALD) is investigated in this study. A developed high-power and high-density multiple inductively coupled plasma (multi-ICP) source is used for a low temperature PE-ALD process. High plasma density and good uniformity are obtained by high power $N_2$ plasma discharge. Silicon nitride films are deposited on a 300-mm wafer using the PE-ALD method at low temperature. To analyze the quality of the SiN and SiCN films, the wet etch rate, refractive index, and growth rate of the thin films are measured. Experiments are performed by changing the applied power and the process temperature ($300-500^{\circ}C$).

• Transactions on Electrical and Electronic Materials
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• v.12 no.2
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• pp.56-59
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• 2011

The characterization of the chemical mechanical polishing (CMP) process for undensified phophosilicate glass (PSG) film is reported using design of experiments (DOE). DOE has been used by experimenters to understand the relationship between the input variables and responses of interest in a simple and efficient way, and it typically is beneficial for determining the appropriatesize of experiments with multiple process variables and making statistical inferences for the responses of interest. The equipment controllable parameters used to operate the machine consist of the down force of the wafer carrier, pressure on the back side wafer, table and spindle speeds (SS), slurry flow (SF) rate, pad condition, etc. None of these are independent ofeach other and, thus, the interaction between the parameters also needs to be understoodfor improved process characterization in CMP. In this study, we selected the five controllable equipment parameters the most recommendedby process engineers, viz. the down force (DF), back pressure (BP), table speed (TS), SS, and SF, for the characterization of the CMP process with respect to the material removal rate and film uniformity in percentage terms. The polished material is undensified PSG which is widely used for the plananization of multi-layered metal interconnects. By statistical modeling and the analysis of the metrology data acquired from a series of $2^{5-1}$ fractional factorial designs with two center points, we showed that the DF, BP and TS have the greatest effect on both the removal rate and film uniformity, as expected. It is revealed that the film uniformity of the polished PSG film contains two and three-way interactions. Therefore, one can easily infer that process control based on a better understanding of the process is the key to success in current semiconductor manufacturing, in which the size of the wafer is approaching 300 mm and is scheduled to continuously increase up to 450 mm in or slightly after 2012.