• The Journal of the Korea institute of electronic communication sciences
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• v.16 no.1
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• pp.69-74
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• 2021

This paper introduces a low-power voltage-controlled oscillator(VCO) with filters that consist of resistors and capacitors. The proposed VCO contains a 5-stage current mode buffer, and each buffer cell has a resistor-capacitor filter that connects input and output terminals. The filter adds a zero to the buffer cell. Because the zero moves the oscillation condition to high frequencies, the proposed VCO can generate a high frequency clock with low power consumption. The proposed circuit has been designed with 0.18 ㎛ CMOS process. The power consumption is 9.83 mW at 2.7 GHz. The proposed VCO shows 3.64 pJ/Hz in our simulation study, whereas the conventional circuit shows 4.79 pJ/Hz, indicating that our VCO achieves 24% reduction in power consumption.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.11 no.5
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• pp.796-805
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• 2000

A 30GHz band low noise amplifier module, which has linear gain of 30dB and noise figure of 2.6dB, for 30GHz satellite communication transponder was developed by use of MMIC and thin film MIC technologies. Two kinds of MMIC circuits were used for the low noise amplifier module, the first one is ultra low noise MMIC circuit and the other is wideband and high gain MMIC circuit. The pHEMT technology with 0.15$mu extrm{m}$ of gate length was applied for MMIC fabrication. Thin film microstrip lines on alumina substrate were used to interconnect two MMIC chips, and the thick film bias circuit board were developed to provide the stabilized DC bias. The input interface of the low noise amplifier module was designed with waveguide type to receive the signal from antenna directly, and the output port was adopted with K-type coaxial connector for interface with the frequency converter module behind the low noise amplifier module. Space qualified manufacturing processes were applied to manufacture and assemble the low noise amplifier module, and space qualification level of environment tests including thermal and vibration test were performed for it. The developed low noise amplifier was measured to show 30dB of minimum gain, $\pm$0.3dB of gain flatness, and 2.6dB of maximum noise figure over the desired operating frequency range from 30 to 31 GHz.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.3
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• pp.358-365
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• 2008

A differential-gain-controlled LNA is designed and implemented in 0.18 um CMOS technology for $3.1{\sim}4.8GHz$ UWB system. In high gain mode, measurements show a differential power gain of $14.1{\sim}15.8dB,\;13.3{\sim}15dB$, respectably, an input return loss higher then 10dB, an input IP3 of -19.3 dBm, a noise figure of $4.85{\sim}5.09dB$, while consuming only 19.8 mW of power from a 1.8V DC supply. In low gain mode, measurements show a differential power gain of $-6.1{\sim}-4.2dB,\;-7.6{\sim}-5.6dB$, respectably, an input return loss higher then 10dB, an input IP3 of -1.45 dBm, a noise figure of $8.8{\sim}10.3dB$, while consuming only 5.4mW of power from a 1.8V DC supply.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.10
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• pp.159-168
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• 2012

In this paper, a W-band single-chip receiver MMIC for FMCW(Frequency-modulated continuous-wave) radar is presented using $0.15{\mu}m$ GaAs pHEMT technology. The receiver MMIC consists of a 4-stage low noise amplifier(LNA), a down-converting mixer and a 3-stage LO buffer amplifier. The LNA is designed to exhibit a low noise figure and high linearity. A resistive mixer is adopted as a down-converting mixer in order to obtain high linearity and low noise performance at low IF. An additional LO buffer amplifier is also demonstrated to reduce the required LO power of the W-band mixer. The fabricated W-band single-chip receiver MMIC shows an excellent performance such as a conversion gain of 6.2 dB, a noise figure of 5.0 dB and input 1-dB compression point($P_{1dB,in}$) of -12.8 dBm, at the RF frequency of $f_0$ GHz, LO input power of -1 dBm and IF frequency of 100 MHz.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.26 no.9
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• pp.783-789
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• 2015

This paper presents a Doherty power amplifier(DPA) operating in the 2.6 GHz band for long term evolution(LTE) systems. In order to achieve high efficiency, second and third harmonic impedances are controlled using a compact output matching network. The DPA was implemented using a gallium nitride high electron mobility transistor(GaN-HEMT) that has many advantages, such as high power density and high efficiency. The implemented DPA was measured using an LTE downlink signal with a 10 MHz bandwidth and 6.5 dB PAPR. The implemented DPA exhibited a gain of 13.1 dB, a power-added efficiency(PAE) of 57.6 %, and an ACLR of -25.7 dBc at an average output power of 33.4 dBm.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.46 no.2
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• pp.141-146
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• 2009

In this paper, a novel harmonic control circuit has been proposed for the design of high-efficiency power amplifier with Si LDMOSFET. The proposed harmonic control circuit haying the short impedances for the second- and third-harmonic components has been used to design the in/output matching network. The efficiency enhancement effect of the proposed harmonic control circuit is superior to the class-F or inverse class-F harmonic control circuit. Also, when the proposed harmonic control circuit has been adapted to the input matching network as well as the output matching network, the of ficiency enhancement effect of the proposed power amplifier has increased all the more. The measured maximum power added efficiency (PAE) of the proposed power amplifier is 82.68% at 1.71GHz band. Compared with class-F and inverse class-F amplifiers, the measured maximum PAE of the proposed power amplifier has increased in $5.08{\sim}9.91%$.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2006.05a
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• pp.607-610
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• 2006

The Digital Frequency Synthesizer(DFS) that generates the wideband signal with hish speed frequency hopping rate and high frequency resolution characteristics was implemented in this paper. The DFS was applied as local oscillator for direct frequency conversion IF modules of DVB-RCS, which directly generates the transmission immediate frequency signal by using DDS and wideband PLL technologies. The DDS technology provides high speed frequency hopping rate and high frequency resolution characteristics, which ate also the DVB-RCS requirement. The wideband PLL technology also provides the wideband signal generation, which is a necessity for direct frequency conversion modules. The implemented DFS provide the spurious suppression characteristic of -50 dBc, frequency resolution of 0.233 Hz and frequency hopping rate of 125 ns, respectively. Also the DFS represent the amplitude flatness of 3 dB and less in the pass-band and phase noise characteristic of -75 dBc/Hz at 1 kHz frequency offset.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.2
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• pp.223-228
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• 2007

The Digital Frequency Synthesizer(DFS) that generates the wideband signal with high speed frequency hopping rate and high frequency resolution characteristics was designed and implemented in this paper The DFS was applied as local oscillator for direct frequency conversion IF modules of DVB-RCS, which directly generates the transmission immediate frequency signal by using DDS and wideband PLL technologies. The DDS technology provides high speed frequency hopping rate and high frequency resolution characteristics, which are also the DVB-RCS requirement. The wideband PLL technology also provides the wideband signal generation, which is a necessity for direct frequency conversion modules. The implemented DFS provides the spurious suppression characteristic of -50 dBc and less, frequency resolution of 0.233 Hz and frequency hopping rate of 125 ns, respectively. Also the DFS represents the amplitude flatness of 3 dB and less in the pass-band, and phase noise characteristic of -75 dBc/Hz at 1 kHz frequency offset.

• Journal of Satellite, Information and Communications
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• v.3 no.1
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• pp.8-14
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• 2008

In this paper, we analyze throughput performance of MF-TDMA scheme and QS MC-DS/CDMA(quasi-synchronous MC-DS/CDMA) scheme based on scrambling on WH sequence and PPGC sequence in early frequency offset caused by high speed transfer terminal. QS MC-DS/CDMA scheme with scrambled WH sequence shows 5.7% higher throughput than MF-TDMA scheme and 8% higher throughput than QS MC-DS/CDMA with PPGC sequence in high speed transfer terminal environment such as maximum 1000Km/h speed with high frequency of Ka-band. Finally, we show that QS MC-DS/CDMA scheme with scrambled WH sequence is more efficient than traditional MF-TDMA scheme at the aspect of throughput in DVB-RCS system with Ka frequency band.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.3
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• pp.236-244
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• 2010

In this paper, a planar structure negative group delay circuit(NGDC) is proposed to overcome the limited availability of the component values required for the prototype lumped element(LE) NGDC design. From the prototype LE circuit analysis, general design equations and the conditions to obtain the NGD are derived and illustrated. Then the LE circuit is converted into the planar structure by applying the transmission line resonator(TLR) theory. As a design example, the LE NGDC and the proposed planar structure NGDC are designed and compared. To estimate the commercial applicability, 2-stage reflection type planar NGDC with -5.6 ns of total group delay, -0.2 dB of insertion loss, and 30 MHz of bandwidth together with 0.1 dB and 0.5 ns of the magnitude and group delay flatness, respectively, for Wideband Code Division Multiple Access(WCDMA) downlink band is fabricated and demonstrated. Also, to show the applicability of the proposed NGDC, we have configured a simple signal cancellation loop and obtained good loop suppression performance.