• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2018.10a
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• pp.514-516
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• 2018

We have investigated the effect of interface trap charge on the characteristics of a monolithic 3D inverter by TCAD simulation. The interface trap charge affects the variation of the threshold voltage and threshold voltage. also The interface trap charge affects the IN/OUT characteristics of the monolithic 3D inverter.

• Proceedings of the KIPE Conference
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• 2007.07a
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• pp.153-155
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• 2007

본 논문에서는 3상 저주파 변압기를 이용한 절연형 멀티레벨 인버터를 위한 새로운 공간 벡터 제어 방식을 제안한다. 제안된 제어 방식은 기존의 미리 계산된 표를 이용한 방식이 아닌 완전히 프로그래밍에 의한 방식으로 구현 시간은 기존 방식에 비해 늘이지 않으며, 확장성이 용의하다는 장점이 있다. 제안된 제어 방식을 공통암을 이용한 3상 IHCML 인버터에 적용하였으며, Matlab을 이용한 시뮬레이션 및 실험실 차원의 인버터 제작을 통하여 제안한 방식의 타당성을 검증 하였다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.5
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• pp.682-687
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• 2022

In this paper, the research results on monolithic three-dimensional integrated-circuit (M3DICs) stacked with tunneling field effect transistors (TFETs) are introduced. Unlike metal-oxide-semiconductor field-effect transistors (MOSFETs), TFETs are designed differently from the layout of symmetrical MOSFETs because the source and drain of TFET are asymmetrical. Various monolithic 3D inverter (M3D-INV) structures and layouts are possible due to the asymmetric structure, and among them, a simple inverter structure with the minimum metal layer is proposed. Using the proposed M3D-INV, this M3D logic gates such as NAND and NOR gates by sequentially stacking TFETs are proposed, respectively. The simulation results of voltage transfer characteristics of the proposed M3D logic gates are investigated using mixed-mode simulator of technology computer aided design (TCAD), and the operation of each logic circuit is verified. The cell area for each M3D logic gate is reduced by about 50% compared to one for the two-dimensional planar logic gates.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.05a
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• pp.200-201
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• 2017

This paper introduces the SPICE simulation results of 3D sequential inverter considering electrical coupling. TCAD data and the SPICE data are compared to verify that the electrical coupling is well considered by using BSIM-IMG for the upper NMOS and LETI-UTSOI model for the lower PMOS. When inter layer dielectric is small, it is confirmed that electrical coupling is well reflected in the top transistor $I_{ds}-V_{gs}$ characteristics according to the change of the bottom transistor gate voltage.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2018.05a
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• pp.173-174
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• 2018

This paper compared the electrical coupling of the monolithic 3D inverter consisting of MOSFET and JLFET. In the case of both the MOSFET and the JLFET, MOSFET and JLFET have a small threshold voltage variation when the thickness of inter-layer dielectric (ILD) = 100 nm. However, when the thickness of ILD = 10 nm, the threshold voltage variation is larger and the JLFET is twice as much as the MOSFET.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.10a
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• pp.614-615
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• 2016

I studied electrical coupling of monolithic 3D inverter(M3D-INV) consisting of Junctionless FET(JLFET). If the thickness of Inter Layer Dielectric (ILD) between top JLFET and bottom JLFET is less than 50nm, current-voltage characteristic of top JLFET is rapidly changed by the gate voltage of bottom JLFET. Therefore, you have to consider about the electrical interaction according to the thickness between top JLFET and bottom JLFET in M3D-INV.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.05a
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• pp.529-530
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• 2017

Electrical coupling of monolithic 3D inverter(M3D-INV) consisting of Junctionless FET(JLFET) was investigated. Depending on the thickness of Inter Layer Dielectirc (ILD) between top and bottom JLFETs, $N_{gate}-N_{gate}$ capacitance and transconductance $g_m$ are changed by the gate voltage of bottom JLFET. Therefore, when using a stacked structure with the ILD below tens nm, AC electrical coupling between two transistors in M3D-INV should be considered.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.11a
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• pp.118-119
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• 2007

High performance three-dimensional (3-D) stacked poly-Si complementary metal-oxide semiconductor (CMOS) inverters with a high quality laser crystallized channel were fabricated. Low temperature crystallization methods of a-Si film using the excimer-laser annealing (ELA) and sequential lateral solidification (SLS) were performed. The NMOS thin-film-transistor (TFT) at lower layer of CMOS was fabricated on oxidized bulk Si substrate, and the PMOS TFT at upper layer of CMOS was fabricated on interlayer dielectric film. The 3-D stacked poly-Si CMOS inverter showed excellent electrical characteristics and was enough for the vertical integrated CMOS applications.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.12
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• pp.2899-2904
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• 2015

This paper introduces about the effect on $I_{DS}-V_{GS}$ characteristic of transistor that interface trap charge is created by damage due to heat in a 3D sequential inverter. A interface trap charge distribution in oxide layer in a 3D sequential inverter is extracted using two-dimensional device simulator. The variation of threshold voltage of top transistor according to the gate voltage variation of bottom transistor is also described in terms of Inter Layer Dielectric (ILD) length of 3D sequential inverter, considering the extracted interface trap charge distribution. The extracted interface trap density distribution shows that the bottom $HfO_2$ layer and both the bottom and top $SiO_2$ layer were relatively more affected by heat than the top $HfO_2$ layer with latest process. The threshold voltage variations of the shorter length of ILD in 3D sequential inverter under 50nm is higher than those over 50nm. The $V_{th}$ variation considering the interface trap charge distribution changes less than that excluding it.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2022.10a
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• pp.118-120
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• 2022

This paper investigated the change of threshold voltage according to the influence of work-function variation (WFV) of metal gate in the device structure of monolithic 3-dimension inverter (M3DINV). In addition, in order to investigate the change in threshold voltage according to the electrical coupling of the NMOS stacked on the PMOS, the gate voltages of PMOS were applied as 0 and 1 V and then the electrical coupling was investigated. The average change in threshold voltage was measured to be 0.1684 V, and they standard deviation was 0.00079 V.