• Title/Summary/Keyword: 2D-to-3D Conversion

Search Result 872, Processing Time 0.028 seconds

Design and Fabrication of a Multi-Function Circuit to Implement Hybrid-Conversion RF Front-End for Broadband and Multiband System (광대역 및 다중 대역 시스템용 혼성 변환 방식 RF 전단부 구현을 위한 다중 기능 회로의 설계 및 제작)

  • Go, Min-Ho;Ju, Young-Rim;Jo, Yun-Hyun;Park, Hyo-Dal
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
    • /
    • v.21 no.3
    • /
    • pp.292-300
    • /
    • 2010
  • In this paper, we propose a RF front-end architecture based on hybrid conversion which is available to receive both broadband and multiband DVB-H receiver, and a multi-function circuit for implementing the RF front-end is fabricated. A multi-function circuit is operated as a sub-harmonic mixer mode in the case of receiving a broadband VHF/UHF band, which show a conversion loss of -10.0 dB, noise figure of 7.0 dB and IIP3 of 2.0 dBm. On the other hand, it is performed as a attenuation mode with a insertion loss of -10.0 dB in receiving a multiband, L-band.

A Novel Frequency Doubler using Feedforward Structure and DGS Microstrip for Fundamental and High-Order Components Suppression (Feedforward 구조와 DGS를 이용하여 기본 신호와 3차 이상의 고조파 신호를 제거한 2차 주파수 체배기 설계)

  • 황도경;임종식;정용채
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
    • /
    • v.14 no.5
    • /
    • pp.513-520
    • /
    • 2003
  • In this paper, a novel design concept of frequency doubler using feedforward technique and DGS microstrip line is proposed. The feedforward loop plays a role of fundamental frequency suppression and DGS microstrip line suppresses over the 3rd order harmonic components. By using this new concept, the high suppression for the undesired signals could be achieved easily. The proposed technique is experimentally demonstrated in 1.87 GHz-to-3.74 GHz frequency doubler. The output power of -3 dBm at the frequency of 3.74 GHz(2f$\_$0/) is measured with 42.9 dB suppression of the fundamental frequency signal(f$\_$0/), 20.2 dB suppression of the 3rd harmonic signal(3f$\_$0/) and B9.7 dB suppression of the 4th harmonic signal(4f$\_$0/). The conversion loss of -2.34 dB ∼ -5.8 dB at the bandwidth of 100 MHz, the phase noise of -97.51 dB/Hz(@10 kHz) were measured.

Design of the Resistive Mixer MMIC with high linearity and LO-RF isolation (고선형성과 높은 LO-RF 격리도를 갖는 새로운 구조의 저항성 Mixer MMIC 설계)

  • Lee, Kyoung-Hak
    • Journal of Satellite, Information and Communications
    • /
    • v.9 no.2
    • /
    • pp.7-11
    • /
    • 2014
  • In this paper, we designed resistive MMIC mixer using $0.5{\mu}m$ p-HEMT process. This Mixer is designed to have a similar performance in -4 ~ 4 dBm local oscillator signal power level and to maintain a constant conversion loss and linear performance due to the variation of local signal. In order to have such characteristics, we designed new feedback circuit topology by using FET, and minimized performance change for LO signal power level variation, also obtain MMIC mixer characteristics which is able to apply in wideband. In the design result, When the LO signal power is -4 ~ 4 dBm, there was 6 dB conversion loss and it came up with the excellent result that IIP3 got over 30 dBm in 0.5 ~ 2.6GHz frequency band.

26GHz 40nm CMOS Wideband Variable Gain Amplifier Design for Automotive Radar (차량용 레이더를 위한 26GHz 40nm CMOS 광대역 가변 이득 증폭기 설계)

  • Choi, Han-Woong;Choi, Sun-Kyu;Lee, Eun-Gyu;Lee, Jae-Eun;Lim, Jeong-Taek;Lee, Kyeong-Kyeok;Song, Jae-Hyeok;Kim, Sang-Hyo;Kim, Choul-Young
    • Journal of IKEEE
    • /
    • v.22 no.2
    • /
    • pp.408-412
    • /
    • 2018
  • In this paper, a 26GHz variable gain amplifier fabricated using a 40nm CMOS process is studied. In the case of an automobile radar using 79 GHz, it is advantageous in designing and driving to drive down to a low frequency band or to use a low frequency band before up conversion rather than designing and matching the entire circuit to 79 GHz in terms of frequency characteristics. In the case of a Phased Array System that uses time delay through TTD (True Time Delay) in practice, down conversion to a lower frequency is advantageous in realizing a real time delay and reducing errors. For a VGA (Variable Gain Amplifier) operating in the 26GHz frequency band that is 1/3 of the frequency of 79GHz, VDD : 1V, Bias 0.95V, S11 is designed to be <-9.8dB (Mea. High gain mode) and S22 < (Mea. high gain mode), Gain: 2.69dB (Mea. high gain mode), and P1dB: -15 dBm (Mea. high gain mode). In low gain mode, S11 is <-3.3dB (Mea. Low gain mode), S22 <-8.6dB (Mea. low gain mode), Gain: 0dB (Mea. low gain mode), P1dB: -21dBm (Mea. Low gain mode).

Broadband Double Balanced Diode Mixer Using a Marchand Balun With Vertical Coupling Structure

  • Nam, Hee;Yun, Tae-Soon;Kwoun, Sung-Su;Hong, Tae-Ui;Lee, Jong-Chul
    • The Journal of The Korea Institute of Intelligent Transport Systems
    • /
    • v.5 no.2 s.10
    • /
    • pp.55-60
    • /
    • 2006
  • In this paper, a broadband double balanced mixer is presented using a wideband Marchand balun implementation by vertical coupler. Frequency is selected as $1.0{\sim}3.7GHz$ for RF, $1.14{\sim}3.84GHz$ for LO, and 140 MHz for IF signals. When LO signal with 7 dBm at 2.64 GHz is injected, a conversion loss of 7.5 dB and RF to LO isolation of -45 dB are obtained. Also, an average conversion loss of 9 dB and RF to LO isolation of -25 dB are obtained for frequency band of $1.0{\sim}3.7GHz$.

  • PDF

Design of Microwave Direct Conversion Receiver Using Sub-Harmonics Pumped Ring Mixer (SHP 링혼합기를 이용한 마이크로파 직접변환 수신기 설계)

  • Kim, Kab-Ki;Kim, Han-Suk;Yoo, Hong-Gil;Lee, Jong-Arc
    • Journal of IKEEE
    • /
    • v.3 no.1 s.4
    • /
    • pp.69-78
    • /
    • 1999
  • In this paper, direct conversion receiver was designed to even harmonic anti-paralled diode pair ring mixer. Using a second harmonic component of LO instead of LO signal and RF signal are mixed by SHP(Sub Harmonic Pumped) mixer with anti-parallel diode pair. Canceling the harmonics of LO signal in ring mixer, SHP mixer using anti-parallel diode pair could mostly reduce the radiation of LO signal through a input port the most, good isolation characteristic, and low spurious characteristic by LO signal was shown over broad band. The produced SHP mixer showed LO/IF, RF/IF and LO/RF isolation was 24.6dB,36.2dB and 22.5dB respectively. And conversion loss was measured 15.6dB, IF output -35.6dBm with -20dBm RF input and 5.5dBm LO signal. 1dB compression point of If signal, in respect to RF signal, was found at the 0dbm RF signal.

  • PDF

High-performance 94 GHz Single Balanced Mixer Based On 70 nm MHEMT And DAML Technology (70 nm MHEMT와 DAML 기술을 이용한 우수한 성능의 94 GHz 단일 평형 혼합기)

  • Kim Sung-Chan;An Dan;Lim Byeong-Ok;Beak Tae-Jong;Shin Dong-Hoon;Rhee Jin-Koo
    • Journal of the Institute of Electronics Engineers of Korea SD
    • /
    • v.43 no.4 s.346
    • /
    • pp.8-15
    • /
    • 2006
  • In this paper, the 94 GHz, low conversion loss, and high isolation single balanced mixer is designed and fabricated using GaAs-based metamorphic high electron mobility transistors (MHEMTs) with 70 nm gate length and the hybrid ring coupler with the micromachined transmission lines, dielectric-supported air-gapped microstrip lines (DAMLs). The 70 nm MHEMT devices exhibit DC characteristics with a drain current density of 607 mA/mm an extrinsic transconductance of 1015 mS/mm. The current gain cutoff frequency ($f_T$) and maximum oscillation frequency ($f_{max}$) are 320 GHz and 430 GHz, respectively. The fabricated hybrid ring coupler shows wideband characteristics of the coupling loss of $3.57{\pm}0.22dB$ and the transmission loss of $3.80{\pm}0.08dB$ in the measured frequency range of 85 GHz to 105 GHz. This mixer shows that the conversion loss and isolation characteristics are $2.5dB{\sim}>2.8dB$ and under -30 dB, respectively, in the range of $93.65GHz{\sim}94.25GHz$. At the center frequency of 94 GHz, this mixer shows the minimum conversion loss of 2.5 dB at a LO power of 6 dBm To our knowledge, these results are the best performances demonstrated from 94 GHz single balanced mixer utilizing GaAs-based HEMTs in terms of conversion loss as well as isolation characteristics.

CMOS Direct-Conversion RF Front-End Design for 5-GHz WLAN

  • Oh, Nam-Jin
    • Journal of electromagnetic engineering and science
    • /
    • v.8 no.3
    • /
    • pp.114-118
    • /
    • 2008
  • Direct-conversion RF front-end for 5-GHz WLAN is implemented in $0.18-{\mu}m$ CMOS technology. The front-end consists of a low noise amplifier, and low flicker noise down-conversion mixers. For the mixer, an inductor is included to resonate out parasitic tail capacitances in the transconductance stage at the operating frequency, thereby improves the flicker noise performance of the mixer, and the overall noise performance of the front-end. The receiver RF front-end has 6.5 dB noise figure, - 13 dBm input IP3, and voltage conversion gain of 20 dB with the power consumption of 30 mW.

A Low-Power 2-Step 8-bit 10-MHz CMOS A/D Converter (저전력 2-Step 8-bit 10-MHz CMOS A/D 변환기)

  • 박창선;손주호;김영랄;김동용
    • Proceedings of the IEEK Conference
    • /
    • 2000.06b
    • /
    • pp.201-204
    • /
    • 2000
  • In this paper, an A/D converter is implemented to obtain 8bit resolution at a conversion rate of 10Msample/s. This architecture is proposed using the 2-step architecture for high speed conversion rate. It is consisted of sample/hold circuit, low power comparator, voltage reference circuit and DAC of binary weighted capacitor array. Proposed A/D converter is designed using 0.2$\mu\textrm{m}$ CMOS technology. The SNR is 45.3dB at a sampling rate of 10MHz with 1.95MHz sine input signal. When an 8bit 10Msample/s A/D converter is simulated, the Differential Nonlinearity / Integral Nonlinearity (DNL/ INL) error are ${\pm}$1 / ${\pm}$2 LSB, respectively. The power consumption is 13㎽ at single +2.5V supply voltage.

  • PDF

A 5.8 GHz SiGe Up-Conversion Mixer with On-Chip Active Baluns for DSRC Transmitter (DSRC 송신기를 위한 능동발룬 내장형 5.8 GHz SiGe 상향믹서 설계 및 제작)

  • Lee Sang heung;Lee Ja yol;Kim Sang hoon;Bae Hyun cheol;Kang Jin yeong;Kim Bo woo
    • The Journal of Korean Institute of Communications and Information Sciences
    • /
    • v.30 no.4A
    • /
    • pp.350-357
    • /
    • 2005
  • DSRC provides high speed radio link between Road Side Equipment and On-Board Equipment within the narrow communication area. In this paper, a 5.8 GHz up-conversion mixer for DSRC communication system was designed and fabricated using 0.8 m SiGe HBT process technology and IF/LO/RF matching circuits, IF/LO input balun circuits, and RP output balun circuit were all integrated on chip. The chip size of fabricated mixer was $2.7mm\times1.6mm$ and the measured performance was 3.5 dB conversion gain, -12.5 dBm output IP3, 42 dB LO to If isolation, 38 dB LO to RF isolation, current consumption of 29 mA for 3.0 V supply voltage.