• Journal of the Korea Institute of Military Science and Technology
• /
• v.14 no.5
• /
• pp.842-849
• /
• 2011

The transponder simulator designed to simulate the transponder of military satellite communication systems in the geostationary orbit is required to have time delay function, because of 250 ms delay time, when a radio wave transmits the distance of 36,000 km in free space. But, it is very difficult to develop 250 ms time delay device in the transponder simulator of 100 MHz bandwidth, due to unstable operation of FPGA, loss of memory data for the high speed rate signal processing. Up to date, bandwidth of the time delay device is limited to 45 MHz bandwidth. To solve this problem, we propose the new time delay techniques up to 100 MHz bandwidth without data loss. Proposed techniques are the low speed down scaling and high speed up scaling methods to read and write the external memory, and the matrix structure design of FPGA memory to treat data as high speed rate. We developed the satellite link simulator in 100 MHz bandwidth using the proposed new time delay techniques, implemented to the transponder simulator and verified the function of 265 ms time delay device in 100 MHz bandwidth.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.5 no.4
• /
• pp.276-281
• /
• 2005

This paper presents a low voltage operating IF QPSK receiver block which is consisted of programmable gain amplifier (PGA) and analog to digital converter. This PGA has 6 bit control and 250MHz bandwidth, $0{\sim}20\;dB$ gain range. Using the proposed PGA architecture (low distortion gain control switch block), we can process the continuous fully differential $0.2{\sim}2.5Vpp$ input/output range and 44MHz carrier with 2 MHz bandwidth signal at 1.8V supply voltage. Using the sub-sampling technique (input freq. is $44{\sim}46MHz$, sampling freq. is 25MHz), we can process the IF QPSK signal ($44{\sim}46MHz$) which is the output of the 6 bit PGA. We can get the SNDR 35dB, which is the result of PGA and ADC at full gain mode. We fabricated the PGA and ADC and the digital signal processing block of the IF QPSK with the 0.18um CMOS MIM process 1.8V Supply.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.13 no.3
• /
• pp.243-250
• /
• 2002

This paper designed a compact printed meandered scot antenna which to integrate in wireless LAN and proposed a printed dual meandered slot antenna for improving bandwidth. A printed dual meandered slot antenna is calculated by using the mehtod of FDTD. The calculated results showed good agreement with the measured results. As a result of measurement, the bandwidth(VSWR< 2) of single meandered slot antenna is 115 MHz and the bandwidth of dual meandered slot antenna is 164 MHz. The dual meandered slot antenna bandwidth has been improves to that of 43% comparing to single meandered slot antenna.

• ETRI Journal
• /
• v.27 no.5
• /
• pp.473-483
• /
• 2005

In this paper, we propose two LC voltage-controlled oscillators (VCOs) that improve both phase noise and tuning range. With both 1/f induced low-frequency noise and low-frequency thermal noise around DC or around harmonics suppressed significantly by the employment of a current-current negative feedback (CCNF) loop, the phase noise in the CCNF LC VCO has been improved by about 10 dB at 6 MHz offset compared to the conventional LC VCO. The phase noise of the CCNF VCO was measured as -112 dBc/Hz at 6 MHz offset from 5.5 GHz carrier frequency. Also, we present a bandwidth-enhanced LC VCO whose tuning range has been increased about 250 % by connecting the varactor to the bases of the cross-coupled pair. The phase noise of the bandwidth-enhanced LC-tank VCO has been improved by about 6 dB at 6 MHz offset compared to the conventional LC VCO. The phase noise reduction has been achieved because the DC-decoupling capacitor Cc prevents the output common-mode level from modulating the varactor bias point, and the signal power increases in the LC-tank resonator. The bandwidth-enhanced LC VCO represents a 12 % bandwidth and phase noise of -108 dBc/Hz at 6 MHz offset.

• The Journal of The Korea Institute of Intelligent Transport Systems
• /
• v.13 no.1
• /
• pp.61-66
• /
• 2014

This paper describes the design, fabrication, and measurement of a compact hexa-band coupling antenna for 4G mobile handset using a small element with two slots. In order to obtain sufficient bandwidth (LTE700, GSM850, GSM900, GSM1800, GSM1900, UMTS) with a Voltage Standing Wave Ratio $(VSWR){\leq}3:1$, two slots are inserted in the small element, and coupling patch is used. The measured result of the fabricated antenna provides 410MHz bandwidth form 0.688 to 1.098GHz and 643 MHz bandwidth form 1.607 to 2.250GHz (${\leq}VSWR 3:1$) with the gain ranging from -0.52 to 4.68 dBi. Also, a good radiation pattern is achieved within the hexa-band (0.698-0.960GHz and 1.710-2.170GHz) range.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.13 no.3
• /
• pp.250-256
• /
• 2002

In this paper, a broadband sleeve monopole antenna using a loading coil in sleeve is proposed. The center frequency of the proposed antenna is 1,990MHz. The antenna of the proposed structure has the same of the single sleeve monopole antenna, except for using the coil instead of the inner conductor in sleeve. As a result, it is found that the bandwidth is 1.239~2.154 GHz(above 53.9 %) for $S_{11}=-10\;d B$(VSWR<2), and the antenna impedance is good for a communication system and feeder which the impedance has 50 Ω.

• Journal of IKEEE
• /
• v.3 no.2 s.5
• /
• pp.186-195
• /
• 1999

In this paper, the RF-modules composed of front-end, frequency synthesizer, modulator/demodulator and power control multi channel WLL personal system for W-CDMA using 10 [MHz] RF channel bandwidth has been implemented and considered. The measured transmission power is 250 [mW] which is very close to the required value. The measured flatness of power at the final output stage is ${\pm}1.5[dB]$ over the required bandwidth of the receiver. In addition, it is found that the chip rate transmitting spread signal is set to 8.192 [MHz], the required rate. The frequencies of RF_LO signal and LO signal of the modulator and the demodulator measured by a frequency synthesizer are satisfied with design requirements. The operating range of the receiving strength signal indicator and AGC units shows 60 [dB] respectively. Also the measured phasor diagram and eye pattern for deciding the RF modules compatible with baseband digital signal processing part are shown good results.

• The Journal of the Acoustical Society of Korea
• /
• v.6 no.3
• /
• pp.43-51
• /
• 1987

In this work an implementation of SAW based serial type AWQPSK modulator is studied. The SAW AWQPSK modulator consisting of input apodized IDT and output uniform IDT with center frequency of 20 MHz and bit rate of 4MHz has been designed and fabricated on $YZ-LiNbO_3$ substrate. Measured center frequency and null-to-null bandwidth are 20MHz, respectively. The sidelobe suppression is achieved 60dB below the peak mainlobe level. Measured responses meet the theoretical values with tolerable amount of deviation. SAW-based modulator simplifies the implementation of AWQPSK which uses complex pulse shape as a baseband pulse.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.41 no.7
• /
• pp.75-79
• /
• 2004

In this paper, a single plane wide band microstrip antenna for integrated circuit as MMIC and LTCC is designed and fabricated. A new configuration for a wide band microstrip antenna with omni-directional pattern is proposed. This antenna consists of two rectangular folded dipoles, which are fed by a coplanar waveguide(CPW). It was effected stabilization ground that a signal plane of CPW feed have been limited ground plane. Therefore, a ground plane of folded structure should be extended outside folded antenna in this research. The characteristics of the proposed antenna were analyzed by using an FDTD methods. The return loss and radiation patterns were simulated and measured. The proposed antenna is get 120MHz bandwidth of PCS band and 250MHz bandwidth of IMT2000 band, used ISM band.

• Journal of the Korea Convergence Society
• /
• v.8 no.7
• /
• pp.1-6
• /
• 2017

This paper presents the design of a frequency measurement device using ADC, EP2AGX FPGA and STM32 processor to accurately measure the frequency of a broadband high frequency signal. The ADC device used in this paper has a sampling frequency of 250 MSPS and a processing frequency bandwidth of 100 MHz. Due to its high sampling frequency, it is difficult to process in ordinary computers or processors, so we implemented the frequency measurement algorithm using the Altra EP2AGX FPGA. The measured frequency is sent to the direction detection controller in real time and fused with the phase signal to calculate the incident azimuth angle of the high frequency signal. The designed frequency measurement device is about 0.2 Mhz in frequency measurement error and 30% less than Anaren DFD-x, which is considered to contribute greatly to the design of radio monitoring and direction detection device.