• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2003.11a
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• pp.53-58
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• 2003

The Wafer Level Packaging is one of the most important technologies in the semiconductor industry today. Its primary advantages are its small form factor and low cost potential for manufacturing including test procedure. The CASIO's WLP samples, application example and the structure are shown in Fig.1, 2&3. There are dielectric layer , under bump metal, re-distribution layer, copper post , encapsulation material and terminal solder .The key technologies are 'Electroplating thick copper process' and 'Unique wafer encapsulation process'. These are very effective in getting electrical and mechanical advantages of package. (Fig. 4). CASIO and CMK are developing a new System Packaging technology called the Embedded Wafer Level Package (EWLP) together. The active components (semiconductor chip) in the WLP structure are embedded into the Printed Wiring Board during their manufacturing process. This new technical approach has many advantages that can respond to requirements for future mobile products. The unique feature of this EWLP technology is that it doesn't contain any solder interconnection inside. In addition to improved electrical performance, EWLP can enable the improvement of module reliability. (Fig.5) The CASIO's WLP Technology will become the effective solution of 'KGD problem in System Packaging'. (Fig. 6) The EWLP sample shown in Fig.7 including three chips in the WLP form has almost same structure wi_th SoC's. Also, this module technology are suitable for RF and Analog system applications. (Fig. 8)

• Asian-Australasian Journal of Animal Sciences
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• v.27 no.8
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• pp.1157-1163
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• 2014

This study was conducted to observe the effects of gas composition in modified atmosphere packaging (MAP) on the shelf-life of Longissimus dorsi of Korean Native Black Pigs-Duroc Crossbred ($KNP{\times}D$) during refrigerated storage. Muscle sample was obtained from the left side of carcass of seven months old of $KNP{\times}D$ barrow. The sample was sliced into 1 cm in thickness, placed on trays (two slices/tray) and filled with different gas composition, i.e. 0:20:80/$O_2:CO_2:N_2$ (MAP1), 30:20:50/$O_2:CO_2:N_2$ (MAP2) and 70:20:10/$O_2:CO_2:N_2$ (MAP3). Other slices of sample were vacuum packed (VP) as a control. All packs were stored at $5{\pm}1^{\circ}C$. At 12 d of storage, pH value of MAP2 and MAP3 were higher (p<0.05) than that of MAP1 and pH value of MAP1 was higher (p<0.05) than that of VP. At 6 d of storage, redness ($a^*$) value of MAP2 and MAP3 were higher (p<0.05) than that of VP and MAP1 and, at 9 and 12 d of storage, redness value of MAP3 was higher (p<0.05) than that of VP, MAP1, and MAP2. At 3, 6, 9, and 12 d of storage, the 2- thiobarbituric acid reactive substances (TBARS) value of MAP3 was higher than that of MAP2 and TBARS value of MAP2 was higher than that of VP and MAP1. At 3, 6, 9, and 12 d of storage, volatile basic nitrogen values of MAP2 and MAP3 were higher (p<0.05) than those of VP and MAP1. At 3 d of storage, total aerobic plate counts of MAP2 and MAP3 were higher (p<0.05) than those of VP and MAP1 and, at 6 d of storage, total aerobic plate counts of MAP3 was higher (p<0.05) than that of MAP1 and MAP2. However, there was no significant different total aerobic plate count among MAP1, MAP2, and MAP3 at 9 and 12 d of storage. There was no significant different total anaerobic plate count among MAP1, MAP2, and MAP3 during storage. It is concluded that the MAP containing 30:20:50/$O_2:CO_2:N_2$ gas composition (MAP2) might be ideal for better meat quality for $KNP{\times}D$ meat.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2002.05a
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• pp.104-108
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• 2002

This paper was investigated the lead free solder characteristics by P mass percentage chang e. Tension test, wetting balance test, spread test, and analysis of intermetallic compound after isothermal aging of Sn-2.5Ag-0.7Cu-0.005P, Sn-2.5Ag-0.7Cu-0.01P, Sn-2.5Ag-0.7Cu-0.02P, Sn-0.7Cu-0.005P were performed for estimation. By adding P on the solder alloys, it was showe d improvement of tensile strength, reduction of intermetallic compound growth and reduction of oxidization of fusible solder under wave soldering processes. After comparing solder alloy containing P with tin lead eutectic solder alloy, p containing solder alloys showed much better solderability than eutectic solder alloys.

• Journal of the Microelectronics and Packaging Society
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• v.20 no.1
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• pp.1-5
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• 2013

Wafer-to-Wafer (W2W) integration technology is an emerging technology promising many benefits, such as reduced size, improved performance, reduced power, lower cost, and divergent integration. As the maturity of W2W technology progresses, new applications will become more viable. However, at present the cost for W2W integration is still very high and both manufacturing yield and reliability issues have not been resolved yet for high volume manufacturing (HVM). Especially for WTW integration resolving compound yield issue can be a key factor for HVM. To have the full benefits of WTW integration technology more than simple wafer stacking technologies are necessary. In this paper, the manufacturing yield for W2W integration is described and the challenges of WTW integration will be discussed.

• Proceedings of the KIEE Conference
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• 2005.07c
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• pp.2395-2397
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• 2005

A low voltage operated piezoelectric RF MEMS in-line switch has been realized by using silicon bulk micromachining technologies for advanced mobile/wireless applications. The developed RF MEMS in-line switches were comprised of four piezoelectric cantilever actuators with an Au contact metal electrode and a suspended Au signal transmission line above the silicon substrate. The measured operation dc bias voltages were ranged from 2.5 to 4 volts by varying the thickness and the length of the piezoelectric cantilever actuators, which are well agreed with the simulation results. The measured isolation and insertion loss of the switch with series configuration were -43dB and -0.21dB (including parasitic effects of the silicon substrate) at a frequency of 2GHz and an actuation voltage of 3 volts.

• Journal of the Microelectronics and Packaging Society
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• v.11 no.1
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• pp.71-76
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• 2004

A compact embedded tapped-line combline filter with interdigital capacitors using low temperature co-fired ceramic (LTCC) technology for wireless application is proposed. Also, in-situ measurement using T-pattern microstrip resonator was performed to acquire exact knowledge of electrical properties of the LTCC substrate. The proposed filter makes it possible to realize a relatively small size, 2.7mm${\times}$2.03mm. by employing interdigital and combline structure. It shows 1.8 ㏈ insertion loss, 37.6㏈ return loss, and 280 MHz bandwidth at the center frequency of 5.09 GHz. Its small size and simple structure make it a good candidate as an integrated filter for various LTCC substrates.

• Journal of the Microelectronics and Packaging Society
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• v.22 no.2
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• pp.5-9
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• 2015

Thermal management becomes serious in 3D stacked IC because of higher heat flux, increased power generation, extreme hot spot, etc. In this paper, we reviewed the recent developments of thermal management for 3D stacked IC which is a promising candidate to keep Moore's law continue. According to experimental and numerical simulation results, Cu TSV affected heat dissipation in a thin chip due to its high thermal conductivity and could be used as an efficient heat dissipation path. Other parameters like bumps, gap filling material also had effects on heat transfer between stacked ICs. Thermal aware circuit design was briefly discussed as well.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2001.07a
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• pp.127-133
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• 2001

Package reliability test was conducted to investigate the effect of solder composition on ball fatigue strength. The specimens are first assembled using eutectic Composition S $n_{62}$P $b_{36}$A $g_2$, S $n_{63}$P $b_{34.5}$A $g_2$S $b_{0.5}$ solder and Pre-conditioned at MRT Lv 2a and then conducted under Temperature Cycle test(TC). For each case, the ball shear strength is obtained and micro structure photos are taken. SEM and EDX are used to analyze failure mechanism. The degradation of shear strength of solder balls after reliability test is discussed.d.

• Journal of the Microelectronics and Packaging Society
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• v.11 no.3 s.32
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• pp.31-36
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• 2004

We charaterized electromagnetic shielding properties of a soft magnetic film using by a ASTM method and 2-port flanged coaxial line method in a RF range and quantitatively analyzed factors for the shielding effectiveness of the soft magnetic film in far field. The shielding effectiveness of the soft magnetic film was dominantly affected by absorption loss not reflection loss in high frequency range of 4-13.5 GHz.

• Journal of the Microelectronics and Packaging Society
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• v.30 no.4
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• pp.8-16
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• 2023

The importance of next-generation packaging technologies is being emphasized as a solution as the miniaturization of devices reaches its limits. To address the bottleneck issue, there is an increasing need for 2.5D and 3D interconnect pitches. This aims to minimize signal delays while meeting requirements such as small size, low power consumption, and a high number of I/Os. Hybrid bonding technology is gaining attention as an alternative to conventional solder bumps due to their limitations such as miniaturization constraints and reliability issues in high-temperature processes. Recently, there has been active research conducted on SiCN to address and enhance the limitations of the Cu/SiO₂ structure. This paper introduces the advantages of Cu/SiCN over the Cu/SiO₂ structure, taking into account various deposition conditions including precursor, deposition temperature, and substrate temperature. Additionally, it provides insights into the core mechanisms of SiCN, such as the role of Dangling bonds and OH groups, and the effects of plasma surface treatment, which explain the differences from SiO₂. Through this discussion, we aim to ultimately present the achievable advantages of applying the Cu/SiCN hybrid bonding structure.