• Journal of the Institute of Convergence Signal Processing
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• v.11 no.4
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• pp.310-319
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• 2010

In this paper, digital watermarking method using wavelet transform and quad-tree algorithm is proposed. The proposed algorithm transforms the input image by DWT(Discrete Wavelet Transform) and AWPT(Adaptive Wavelet Packet Transform), inserts the watermark by quad-tree algorithm and the Cox's algorithm. The simulation for performance analysis of the proposed algorithm is implemented about the effect of embedding watermark in each subband coefficient (HH, LH, HL) of DWT, each DWT level, and each AWPT level. The simulation result by using DWT is compared with that using AWPT in the proposed algorithm. In addition, the effect of embedding watermark in the lowest frequency band (LL) is simulated. As a simulation result using DWT, the watermarking performance of simultaneously embedding in HH, LH, and HL band of DWT(6 level) is better than that of different cases. The result of AWPT(3 level) improves the correlation value compared to that of DWT(3 level). In addition, insertion the watermark to the LL band about 30~60% of all watermarks improves the correlation value while PSNR performance decreases 1~2dB.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.931-934
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• 2003

DWT(Discrete Wavelet Transform)를 2차원 하드웨어로 구현하기 위해서 많은 하드웨어와 실행시간이 들기 때문에 효율적인 구조가 중요하다. 그래서, 이 논문에서는 2차원 DWT에 대한 효율적인 하드웨어 이용률과 크기의 감소, 완벽한 레지스터 이용률, 규칙적인 데이터 흐름으로 필터 길이의 확장을 쉽게 할 수 있도록 구조를 개선하고, 개선된 구조를 VHDL로 검증하였다.

• Journal of Digital Contents Society
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• v.5 no.2
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• pp.128-132
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• 2004

In this paper, a Fuzzy Inference System(FIS) based watermarking algorithm in Discrete Wavelet Transform(DWT) domain is proposed. A 2D fuzzy inference values, in which the inputs are parameters of the coefficients of the DWT block of the original image and the output is strength of watermark embedded, is devised. The fuzzy inference algorithm guarantees that the watermark to be embedded into the original image adaptively. The experimental results shows that proposed approach is robust to the digital image processing schemes.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.40 no.2
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• pp.17-25
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• 2003

In this paper, a processor architecture is proposed based on the state space implementation technique for real time processing of 2-D discrete wavelet transform(DWT). It conducts 2-D DWT operations in consideration of row and column direction simultaneously, thus can reduce latency due to memory access for storing intermediate results. It is a VLSI architecture suitable for real time processing. The proposed architecture includes only four multipliers and four adders, and NK-N internal memory storage, where K denotes the length of filter. It has a small hardware complexity. Therefore it is very suitable architecture for real time, embedded applications such as web camera server. Since the processor is easily extended to array structure, it can be applied to various image processing applications.

• Journal of the Korean Society for Marine Environment & Energy
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• v.1 no.2
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• pp.82-95
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• 1998

In this paper, two series of numerical simulations are performed using LS/DYNA3D: The first series of numerical simulations are collision events between a 310,000 DWT double hull VLCC (struck ship) and two 35,000 and 105,000 DWT tankers (striking ships). Collisions are assumed to occur at the middle of the VLCC with the striking ships moving at right angle to the YLCC centerline. The second ones, grounding accidents of two 40,000 DWT Conventional and Advanced Double Hull lanker bottom structures, CONV/PD328 and ADH/PD328 models. The overall objective of this study is to understand the structural failure and energy absorbing mechanisms during collision and grounding events for double hull tanker side and bottom structures, which lead to the initiation of inner shell rupture and cause the kinetic energy dissipation to bring the ship to a stop. These numerical simulations will contribute to the estimation of damage extents of collision and grounding accidents and the future improvements in lanker safety at the design stage.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.6A
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• pp.618-627
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• 2002

In processing images using 2 dimensional Discrete Wavelet Transform(2D-DWT), the method to process the pixels around the image boundary may affect the quality of image and the cost to implement in hardware and software. This paper proposed an effective method to treat the boundary pixels, which is apt to implement in hardware and software without losing the quality of the image costly. This method processes the 2-D image as 1-D array so that 2-D DWT is performed by considering the image with the serial-sequential data structure (Serial-Sequential Processing). To show the performance and easiness in implementation of the proposed method, an image compression codec which compresses image and reconstructs it has been implemented and experimented. It included log-scale fried quantizer, but the entropy coder was not implemented. From the experimental results, the proposed method showed the SNR of almost the same SNR(Signal to Noise Ratio) to the Periodic Expansion(PE) method when the compression ratio(excluding entropy coding) of 2:1, 15.3% higher than Symmetric Expansion(SE) method, and 9.3% higher than 0-pixel Padding Expansion(ZPE) method. Also PE method needed 12.99% more memory space than the proposed method. By considering only the compression process, SE and ZPE methods needed additional operations than the proposed one. In hardware implementation, the proposed method in this paper had 5.92% of overall circuit as the control circuit, while SE, PE, and ZPE method has 22%, 21,2%, and 11.9% as the control circuit, respectively. Consequently, the proposed method can be thought more effective in implementing software and hardware without losing any image quality in the usual image processing applications.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.8B
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• pp.1119-1128
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• 2001

본 논문에서는 이차원(2-D) 이산 웨이블릿 면환(Discrete Wavelet Transform, DWT)을 이용한 연상압축기를 FPGA 칩에서 실시간으로 동작 가능하도록 하는 효율적인 메모리 스케줄링 방법(E$^2$M$^2$)을 제안하였다. S/W적으로 위의 메모리 사상 방법을 검증한 후, 실제로 상용화된 SFRAM을 선정하여 메모리 제어기를 구현하였다. 본 논문에서는 Mallet-tree를 이용한 2-D DWT 영상압축 칩을 구현할 경우를 가정하였다. 이 알고리즘은 연산 과정에서 많은 데이터를 정장하여야 하는데, FPGA는 많은 데이터를 저장할 수 있는 메모리가 내장되어 있지 않으므로 외부 메모리를 사용하여야 한다. 외부메모리는 열(row)에 대해서만 연속(burst) 읽기, 쓰기 동작이 가능하기 때문에 Mallet-tree 알고리즘의 데이터 입출력을 그대로 적용할 경우 실시간 동작을 수행하는 DWT 압축 칩을 구현할 수 없다. 본 논문에서는 데이터 쓰기를 수행할 경우에는 메모리 셀(cell)의 수직 방향을 저장시키고 읽기를 수행할 때는 수평으로 데이터의 연속 읽기를 수행함으로써 필터가 항상 수평 방향에 위치하게 하는 방법을 제안하였다. 입방법을 C-언어로 DWT 커넬(Kernel)과 메모리의 에뮬레이터(emulator)를 구현하여 실험한 결과, Mallat-tree 이론을 그대로 적용시켰을 때와 동일한 필터링을 수행할 수 있음을 검증하였다. 또한, 상용화된 SDRAM의 메모리 제어기를 H/W로 구현하여 시뮬레이션 함으로써 본 논문에서 제안한 방법이 실제적인 하드웨어로 실시간 동작을 할 수 있음을 보였다.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.40 no.5
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• pp.332-346
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• 2003

In this paper, a system which can compress and reconstruct the digital image was implemented using 2 dimensional DWT(Discrete Wavelet Transform). The proposed system consists of the FPGA board tocompress the image and the application software(S/W) to reconstruct it. First the FPGA receives the image from AID converter and compresses the image using wavelet transform. The compressed data is transferred into the PC using the PCI interface. The compressed image is reconstructed by an application S/W inside the PC. The image compressor can compress about 60 fields per second, in which the image format was NTSC YCbCr(4:2:2) and the image size was 640${\times}$240 pixels per field. The designed hardware mapped into one FPGA occupying 11,120 LAB (Logic Array Block) and 27,456 ESB(Embedded System Block) in APEX20KC EP20K1000B652-7. It globally uses 33MHz clock and the memory control part uses 100MHz.

• Journal of Korea Society of Digital Industry and Information Management
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• v.7 no.4
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• pp.119-131
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• 2011

In this paper, we explore the application of 2-D dual-tree discrete wavelet transform (DDWT), which is a directional and redundant transform, for image coding. DDWT main property is a more computationally efficient approach to shift invariance. Also, the DDWT gives much better directional selectivity when filtering multidimensional signals. The dual-tree DWT of a signal is implemented using two critically-sampled DWTs in parallel on the same data. The transform is 2-times expansive because for an N-point signal it gives 2N DWT coefficients. If the filters are designed is a specific way, then the sub-band signals of the upper DWT can be interpreted as the real part of a complex wavelet transform, and sub-band signals of the lower DWT can be interpreted as the imaginary part. The quincunx lattice is a sampling method in image processing. It treats the different directions more homogeneously than the separable two dimensional schemes. Quincunx lattice yields a non separable 2D-wavelet transform, which is also symmetric in both horizontal and vertical direction. And non-separable wavelet transformation can generate sub-images of multiple degrees rotated versions. Therefore, non-separable image processing using DDWT services good performance.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.54 no.2
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• pp.124-130
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• 2005

In this paper, low-power design and implementation techniques for DWT(Discrete Wavelet Transform) of the JPEG2000 compression are proposed. In DWT block of the JPEG2000, linear phase 9 tap and 7 tap filters are used. For low-power implementation of those filters, processor technique for DA(Distributed Arithmetic) filter and minimization technique for number of addition in CSD(Canonic Signed Digit) filter are utilized. Proposed filter structure consists of 3 blocks. In the first CSD coefficient block, every possible 4 bit CSD coefficients are calculated and stored. In second processor block, multiplication is done by MUX and addition processor in terms of the binary values of filter coefficient. Finally, in third block, multiplied values are output and stored in flip-flop train. For comparison of the implementation area and power dissipation, proposed and conventional structures are implemented by using Verilog-HDL coding. In simulation, it is shown that 53.1% of the implementation area can be reduced comparison with those of the conventional structure.