• Journal of the Institute of Convergence Signal Processing
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• v.9 no.4
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• pp.321-328
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• 2008

In this paper, we propose the hardware architecture of two-dimensional discrete wavelet transform (2D DWT) and quantization for using JPEG2000. Color 2-D DWT processor is proposed that is to apply to JPEG 2000 Hard-wired Encoder. JPEG 2000 DWT processor uses the Daubechies' (9,7) bi-orthogonal filter, and we design by minimizing error of the DWT transformer by ${\pm}1$ LSB during compression and decompression. We designed the DWT filters that using by using shift and adder structure instead of multiplier structure which raise the hardware complexity. It is improve the operation speed of filters and reduce the hardware complexity. The proposed system is designed by the hardware description language Verilog-HDL and verified by Synopsys Design Analyzer using TSMC 0.25${\mu}m$ ASIC library.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1157-1160
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• 1998

This paper describes the design of a block data flow architecture(BDFA) which implements 2-D discrete wavelet transform(DWT)/inverse discrete wavelet transform(IDWT) for real time image processing applications. The BDFA uses 2-D product separable filters for DWT/IDWT. It consists of an input module, a processor array, and an output module. It use both data partitioning and algorithm partitioning to achieve high efficiency and high throughput. The 2-D DWT/IDWT algorithm for 256$\times$256 lenna image has been simulated using IDL(Interactive Data Language). The 2-D array structured BDFA for the 2-D filter has been modeled and simulated using VHDL.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.7
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• pp.518-525
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• 2003

In this paper, we present a fast hardware architecture to implement a parallel 2-dimensional discrete wavelet transform(DWT)based on the lifting scheme DWT framework. The conventional 2-D DWT had a long initial and total latencies to get the final 2D transformed coefficients because the DWT used an entire input data set for the transformation and transformed sequentially The proposed architecture increased the parallel performance at computing the row directional transform using new data splitting method. And, we used the hardware resource sharing architecture for improving the total throughput of 2D DWT. Finally, we proposed a scheduling of hardware resource which is optimized to the proposed hardware architecture and splitting method. Due to the use of the proposed architecture, the parallel computing efficiency is increased. This architecture shows the initial and total latencies are improved by 50% and 66%.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.34S no.10
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• pp.132-140
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• 1997

This paper proposes systolic array architectures for compuataion of the 1-D and 2-D discrete wavelet transform (DWT). The proposed systolic array for compuataion of the 1-D DWT consists of L processing element (PE) arrays, where the PE array denotes the systolic array for computation of the one level DWT. The proposed PE array computes only the product terms that are required for further computation and the outputs of low and high frequency filters are computed in alternate clock cycles. Therefore, the proposed architecuter can compute the low and high frequency outputs using a single architecture. The proposed systolic array for computation of the 2-D DWT consists of two systolic array architectures for comutation of the 1-D DWT and memory unit. The required time and hardware cost of the proposed systolic arrays are comparable to those of the conventional architectures. However, the conventional architectures need extra processing units whereas the proposed architectures fo not. The proposed architectures can be applied to subband decomposition by simply changing the filter coefficients.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37A no.11
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• pp.993-1000
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• 2012

In this research, we proposed an efficient VLSI architecture of the lifting-based 2D DWT (Discrete Wavelet Transform) filter with 100% hardware utilization. The (9,7) filter structure has been applied and extendable to the filter length. We proposed a new block-based scheduling that computes the DWT for the lower levels on an "as-early-as-possible" basis, which means that the calculation for the lower level will start as soon as the data is ready. Since the proposed 2D DWT computes the outputs of all levels by one row-based scan, the intermediate results for other resolution levels should be kept in storage such as the Data Format Converter (DFC) and the Delay Control Unit (DCU) until they are used. When the size of input image is $N{\times}N$ and m is the filter length, the required storage for the proposed architecture is about 2mN. Since the proposed architecture processes the 2D DWT in horizontal and vertical directions at the same time with 4 input data, the total period for 2D DWT is $N^2(1-2^{-2J})/3$.

• Journal of IKEEE
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• v.6 no.1 s.10
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• pp.80-86
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• 2002

This paper presents a fast hardware architecture to implement a 2-D DWT(Discrete Wavelet Transform) computed by lifting scheme framework. The conventional 2-D DWT hardware architecture has problem in internal memory, hardware resource, and latency. The proposed architecture was based on the 4-way partitioned data set. This architecture is configured with a pipelining parallel architecture for 4-way partitioning method. Due to the use of this architecture, total latency was improved by 50%, and memory size was reduced by using lifting scheme.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.12
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• pp.39-47
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• 2010

This paper proposes a fully-utilized block-based 2D DWT architecture, which consists of four 1D DWT filters with two-channel QMF PR Lattice structure. For 100% hardware utilization, we propose a new method which processes four input values at the same time. On the contrary to the image-based 2D DWT which requires large memories, we propose a block-based 2D DWT so that we only need 2MN-3N of storages, where M and N stand for filter lengths and width of the image respectively. Furthermore, the proposed architecture processes in horizontal and vertical directions simultaneously so that it computes the DWT for an $N{\times}N$ image within a period of $N^2(1-2^{-2J})/3$. Compared to existing approaches, the proposed architecture shows 100% of hardware utilization and high throughput rate. However, the proposed architecture may suffer from the long critical path delay due to the cascaded lattices in 1D DWT filters. This problem can be mitigated by applying the pipeline technique with maximum four level. The proposed architecture has been designed with VerilogHDL and synthesized using DongbuAnam $0.18{\mu}m$ standard cell.

• Proceedings of the IEEK Conference
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• 2001.06d
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• pp.105-108
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• 2001

This paper proposed an efficient memory scheduling method (E$^2$M$^2$) by which the real-time image compression using 2-dimensional discrete wavelet transform(2-D DWT) is possible in an FPGA chip. In this paper, we assumed that the 2-D DWT was performed as the Mallat-tree. After the memory mapping method was proved in software, the memory controller was designed for an commercial SDRAM IC.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.37 no.1
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• pp.59-68
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• 2000

This paper proposes efficient VLSI architectures for computation of the 2- D discrete wavelet transform (DWT). The two proposed VLSI architectures for the 2- D DWT are constructed based on block-based computation Each $M{\times}N$ ($N{\times}M$) block DWT is performed along the row (column) direction simultaneously, where M and N denote the number of filter taps and the number of columns (rows), respectively The proposed architectures compute the lowpass and highpass output sequences of the 1 - DWT along the row and column directions using a single architecture In alternate clock cycles Therefore the extra processing units required for the proposed architectures are much smaller than those of the conventional architectures They are modeled In very high speed Integrated circuit hardware description language (HIDL) and Simulated to show their functional validity.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.50 no.10
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• pp.473-478
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• 2001

Image processings using the two-dimensional wavelet transform (2DWT) have been a very active research area in recent years because the 2DWT possess many good properties. However, the discrete 2DWT can not be used for pattern recognition directly because it does not have the translation property. In this paper, we show why conventional discrete two-dimensional wavelet transforms cannot be used for pattern recognitions directly. Then, we propose a new method that makes it possible to use discrete 2DWT to pattern recognition without modification of standard pyramidal algorithms. The main idea of our method is to postprocess the wavelet transformed images using the second-order neural network. To justify the validity of the method, evaluations with test images were performed. The effectiveness of the method can be shown by the evaluation results.