• Journal of Biomedical Engineering Research
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• v.10 no.1
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• pp.1-10
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• 1989

An automatic lung nodule detection algorithm was applied for digital radiographic images using Bit Slice Processor. In this algorithm, signal enhancing filtering and signal suppressing filtering were performed on the given digital chest image, respectively. Then we grit the dirt- frrence image from these filtered images, and hi-level island images were obtained by applying various threshold values. From the island images, we decided the suspicious nodules using size and circularity test, and marked them to alert radiologists. The performance of the atgorithm was analyzed with respect to the size, contrast and position of digitally synthesized nodules. This method presented 45.8% of true positive ratio for the nodules of lOw in diameter with 12-16 pixel value differnces.

• Proceedings of the KIEE Conference
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• summer
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• pp.1269-1271
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• 2004

This is a thesis experiment result which is reported with using 16-Bit microprocessor H8 series of Renesas company, organizing digital control which is practicable PWM embodiment, and applying switched-mode power supply. The basic topology consists of the active clamp forward DC-DC converter which is widely used for the highly efficient power supply these days. In an experiment, it incites the result to lay emphasis on the highly efficient operation of converter, and performance of digital control which is practicable PWM embodiment. And it is debated on performance of processor and condition for improving performance of part.

• Proceedings of the KIEE Conference
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• 2001.07d
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• pp.2051-2053
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• 2001

기존의 Passenger Boarding Bridge Controller는 PLC Type Controller 등으로 복합적으로 구성하는데 본 연구에서는 16bit Micro Processor를 이용한 전용 콘트롤러를 적용해 각종 고급기능을 부여하고, 안전하고 유연한 운전이 가능하도록 하였고 기존의 수동 운전에 필요한 각종 조작 스위치를 부가하였으며, TFT LCD Color Display 및 Touch Screen을 장착하여 자동 운전을 위한 각종 조작이 용이하도록 하여 유지관리에 필요한 각종정보를 화면상에 표시하여 조작자로 하여금 PBBC(Passenger Boarding Bridge Controller)의 각종상태를 쉽고 빠르게 파악 할 수 있도록 시뮬레이터를 설계 및 제작을 하였다. 그 결과 기존의 방식보다 성능면은 비슷하였고 기능면에서는 다양하게 기능을 검정을 할 수가 있었다. 향후 연구 지속시 다양한 개선이 되라 보아진다.

• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.1
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• pp.101-113
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• 1986

In this paper, a real-time pitch detector LPC vocoder as implemented on a high speed digital signal processor, NEC 7720, is described. The pitch detector was based mainly on the SIFT algorithm. The SIFT pitch detector consists primarily of a digital low pass filter, inverse filter, computation of autocorrelation, a peak picker, interpolation, V/UV defcision and a final pitch smoother. In our approach, modification, mainly on the V/UV decision and a final pitch smoother, was made to estimate more accurate pitches. An 16-bit fixed-point aithmatic was employed for all necessary computation and the simulated results were compared with the eye detected pitches obtained from real speech data. The pitch detector occupies 98.8% of the instruction ROM, 37% of the data ROM, and 94% of internal RAM and takes 15.2ms to estimate a pitch when an analysis frame is consisted of 128 sampled speech data. It is observed that the tested results were well agreed with the computer simulation results.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.11
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• pp.2517-2524
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• 2012

This paper describes an efficient implementation of KS(Korea Standards) block cipher algorithm ARIA. The ARIA crypto-processor supports three master key lengths of 128/192/256-bit and four modes of operation including ECB, CBC, OFB and CTR. A hardware sharing technique, which shares round function in encryption/decryption with key initialization, is employed to reduce hardware complexity. It reduces about 20% of gate counts when compared with straightforward implementation. The ARIA crypto-processor is verified by FPGA implementation, and synthesized with a $0.13-{\mu}m$ CMOS cell library. It has 46,100 gates on an area of $684-{\mu}m{\times}684-{\mu}m$ and the estimated throughput is about 1.28 Gbps at 200 MHz@1.2V.

• Journal of Biomedical Engineering Research
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• v.18 no.4
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• pp.467-476
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• 1997

This paper presents a designing of a digital hearing aid processor (DHAP) chip being operated by a dedicated DSP core. The DHAP for hearing aid devices must be feasible within a size and power consumption required. Furthermore, it should be able to compensate for wide range of hearing losses and allow sufficient flexibility for the algorithm development. In this paper, a programmable 16-bit fixed-point DSP core is employed thor the designing of the DHAP. The designed DHAP performs a nonlinear loudness correction of 8 frequency bands based on audiometric measurements of impaired subjects. By employing a programmable DSP, the DHAP provides all the flexibility needed to implement audiological algorithms. In addition, the chip has low-power feature and $5, 500\times5000$$\mu$$m^2$ dimensions that fit for wearable hearing aids.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.46 no.3
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• pp.119-124
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• 2009

In this paper, AMR-WB+ audio coder is implemented, in real-time, using Intel 400MHz Xscale PXA250 with 32bit RISC processor ARM9E-J(R)core. The assembly code for ARM9E-J(R)core is developed through the serial process of C code optimization, cross compile, assembly code manual optimization and adjusting the optimized code to Embedded Visual C++ platform. C code is trimmed on Visual C++ platform. Cross compile and assembly code manual optimization are performed on CodeWarrior with ARM compiler. Through these stages the code for both ARM EVM board and PDA is implemented. The average complexities of the code are 160.75MHz on encoder and 33.05MHz on decoder. In case of static link library(SLL), the required memories are 65.21Kbyte, 32.01Kbyte and 279.81Kbyte on encoder, decoder and common sources, respectively. The implemented coder is evaluated using 16 test vectors given by 3GPP to verify the bit-exactness of the coder.

• Journal of KIISE:Software and Applications
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• v.32 no.3
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• pp.227-235
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• 2005

In the embedded system domain, both memory requirement and energy consumption are great concerns. To save memory and energy, the 32 bit ARM processor supports the 16 bit Thumb instruction set. For a given program, the Thumb code is typically smaller than the ARM code. However, the limitations of the Thumb instruction set can often lead to generation of poorer quality code. To generate codes with smaller size but a little slower execution speed, Krishnaswarmy suggests a profiling guided selection algorithm at module level for generating mixed ARM and Thumb codes for application programs. The resulting codes of the algorithm give significant code size reductions with a little loss in performance. When the instruction set is selected at module level, some functions, which should be compiled in Thumb mode to reduce code size, are compiled to ARM code. It means we have additional code size reduction chance. In this paper, we propose a profile guided selection algorithm at function level for generating mixed ARM and Thumb codes for application programs so that the resulting codes give additional code size reductions without loss in performance compared to the module level algorithm. We can reduce 2.7％ code size additionally with no performance penalty

• The Journal of the Acoustical Society of Korea
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• v.20 no.1
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• pp.56-61
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• 2001

This paper presents the real-time implementation of an AMR (Adaptive Multi Rate) vocoder which is included in the asynchronous International Mobile Telecommunication (IMT)-2000 mobile ASIC. The implemented AMR vocoder is a multi-rate coder with 8 modes operating at bit rates from 12.2kbps down to 4.75kbps. Not only the encoder and the decoder as basic functions of the vocoder are implemented, but VAD (Voice Activity Detection), SCR (Source Controlled Rate) operation and frame structuring blocks for the system interface are also implemented in this vocoder. The DSP for AMR vocoder implementation is a 16bit fixed-point DSP which is based on the TeakLite core and consists of memory block, serial interface block, register files for the parallel interface with CPU, and interrupt control logic. Through the implementation, we reduce the maximum operating complexity to 24MIPS by efficiently managing the memory structure. The AMR vocoder is verified throughout all the test vectors provided by 3GPP, and stable operation in the real-time testing board is also proved.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.9A
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• pp.931-939
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• 2007

This paper describes the system which automatically generates instruction-set simulators cores using the SMDL. SMDL describes structure and instruction-set information of a target DSP machine. Analyzing behavioral information of each pipeline stage of all instructions on a target ASIPS, the proposed system automatically generates a cycle-accurate instruction set simulator in C++ for a target processor. The proposed system has been tested by generating instruction-set simulators for ARM9E-S, ADSP-TS20x, and TMS320C2x architectures. Experiments were performed by checking the functions of the $4{\times}4$ matrix multiplication, 16-bit IIR filter, 32-bit multiplication, and the FFT using the generated simulators. Experimental results show the functional accuracy of the generated simulators.