• 분석과학
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• 제24권5호
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• pp.387-394
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• 2011

본 연구에서는 국내 유해폐기물의 효율적인 관리를 위해 도료공정에서 발생한 폐기물 중 미규제 중금속의 배출특성을 조사하였다. 사업장은 올바로시스템에 등록된 폐기물 배출업체를 대상으로, 유럽의 도료공정(European Waste Catalogue, EWC 08)과 유사한 폐기물 발생 업체로 하였으며 조사대상 사업장 64개 업체를 현지 방문하여 원료, 생산제품, 생산 공정, 폐기물의 종류 및 배출과정을 조사하고 생산 공정에서 배출되는 73개의 폐기물을 채취하였다. 모든 시료에 대하여 함량 분석을 수행하였고, 특히 고상시료 16건에 대해서는 중금속 8항목(Ba, Be, F, Ni, Sb, Se, V, Zn)에 대한 용출분석을 수행하였다. 도료공정에서 발생된 폐기물 중 ICP-MS를 이용한 Ba의 함량분석 결과는 ND (Not Detected)~44,973.00 mg/kg의 농도 범위를 나타내었다. 특히 폐페인트 시료 7건, 폐수처리오니 2건, 공정오니 1건 및 폐유기용제 1건에서 Ba이 제안기준인 500 mg/kg을 초과하였으며 나머지 미규제 항목은 검출되지 않았다.

• 대한전자공학회논문지SD
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• 제47권3호
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• pp.7-17
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• 2010

본 논문은 4-트랜지스터 래치 셀을 이용한 저전력향 신개념의 SRAM을 제안한다. 4-트랜지스터 메모리 셀은 종래의 6-트랜지스터 SRAM 셀에서 access 트랜지스터를 제거한 형태로, PMOS 트랜지스터의 소스는 비트라인 쌍에 연결되고 NMOS 트랜지스터의 소스는 두개의 워드라인에 각각 연결된다. 동작시 워드라인에 일정크기의 전압을 인가할 때 비트라인에 흐르는 전류를 감지하여 읽기동작을 수행하고, 비트라인 쌍에 전압차이를 두고 워드라인에 일정크기의 전압을 인가하여 쓰기동작을 수행한다. 이는 공급전압 보다 낮은 소신호 전압으로 워드라인과 비트라인을 구동하여 메모리 셀의 데이터를 저장하고 읽어낼 수 있어서 동작 소비전력이 적다. 아울러 셀 누셀전류 경로의 감소로 인해 대기 소모전력 또한 개선되는 장점이 있다. 0.18-${\mu}m$ CMOS 공정으로 1.8-V, 16-kbit SRAM test chip을 제작하여 제안한 회로기술을 검증하였고, 칩 면적은 $0.2156\;mm^2$이며 access 속도는 17.5 ns 이다. 동일한 환경에서 구현한 종래의 6-트랜지스터 SRAM과 비교하여 읽기동작시 30% 쓰기동작시 42% 동작소비전력이 적고, 대기전력 또한 64% 적게 소비함을 관찰하였다.

• 대한전자공학회논문지TC
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• 제47권12호
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• pp.84-89
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• 2010

본 논문에서는 마이크로스트립 사각 개방 루프 이중 Split Ring 공진기를 이용하여 전압 제어 발진기의 위상 잡음 특성을 줄이기 위한 새로운 구조를 제안하였다. 이러한 특성 실현을 위하여 마이크로스트립 사각 개방 루프의 형태를 갖는 사각 형태의 이중 Split Ring 공진기에 대하여 연구하였다. 일반적인 마이크로스트립 선로 공진기뿐만 아니라 위상 잡음 특성을 개선하기 위하여 제안된 마이크로스트립 사각 개방 루프 공진기와 마이크로스트립 사각 개방 루프 Split Ring 공진기와 비교할 경우에도 마이크로스트립 사각 개방 루프 이중 SRR는 더 큰 결합 계수를 갖으며, 이로 인하여 얻을 수 있는 더 높은 Q 값을 통하여 전압 제어 발진기의 위상 잡음을 줄 일 수 있다. 1.7V의 공급 전력을 갖는 전압 제어 발진기는 주파수 조절 범위, 11.74~11.75 GHz에서 -123.2~-122.0 dBc/Hz @ 100 kHz의 위상 잡을 특성을 갖는다. 이 전압 제어 발진기의 Figure Of Merit (FOM)은 동일한 주파수 조절 범위에서 -214.8~-221.7 dBc/Hz @ 100 kHz를 갖는다. 기본적인 마이크로스트립 선로 공진기, 마이크로스트립 사각 개방 루프 공진기와 비교할 경우, 제안된 공진기를 이용한 전압 제어 발진기의 위상 잡음 특성은 각각 26 dB, 10 dB 개선되었다.

• 대한전자공학회논문지TC
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• 제44권7호통권361호
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• pp.41-46
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• 2007

본 논문은 두 개의 공통 게이트 증폭단을 사용한 캐스코형 CMOS 저잡음 증폭기의 후치 선형화 기법을 제안한다. 제안된 기법은 두 개의 공통 게이트 FET 단을 사용하며, 한 FET는 공통 소스단에서 전달된 전류 성분 중 선형 전류 성분만을 부하에 전달하고, 다른 한 단은 3차 혼변조 전류를 흡수하도록 동작한다. 선형 전류 성분과 혼변조 전류 성분을 선택적으로 분류하기 위해 $0.18{\mu}m$ CMOS 공정에서 제공되는 후막 (thick oxide) FET를 혼변조 전류 흡수용 FET로, 박막 (thin oxide) FET를 선형 전류 버퍼로 사용하였다. 제안된 방법을 검증하기 위해 $0.18{\mu}m$ CMOS 공정을 이용하여 2.14GHz에서 동작하는 저잡음 증폭기를 설계하였다. 제작된 차동 증폭기는 1.8V 전원에서 12.4mA를 소모하며, 측정 결과로 11 dBm IIP3, 15.5 dB 전력이득, 그리고 2.85 dB 잡음지수를 특성을 얻었다. 이는 후치 선형화가 없는 회로에 비해 7.5dB의 $IIP_{3}$ 개선된 결과이다.

• ETRI Journal
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• 제26권3호
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• pp.229-240
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• 2004

This paper reports on our development of a dual-mode transceiver for a CMOS high-rate Bluetooth system-onchip solution. The transceiver includes most of the radio building blocks such as an active complex filter, a Gaussian frequency shift keying (GFSK) demodulator, a variable gain amplifier (VGA), a dc offset cancellation circuit, a quadrature local oscillator (LO) generator, and an RF front-end. It is designed for both the normal-rate Bluetooth with an instantaneous bit rate of 1 Mb/s and the high-rate Bluetooth of up to 12 Mb/s. The receiver employs a dualconversion combined with a baseband dual-path architecture for resolving many problems such as flicker noise, dc offset, and power consumption of the dual-mode system. The transceiver requires none of the external image-rejection and intermediate frequency (IF) channel filters by using an LO of 1.6 GHz and the fifth order onchip filters. The chip is fabricated on a $6.5-mm^{2}$ die using a standard $0.25-{\mu}m$ CMOS technology. Experimental results show an in-band image-rejection ratio of 40 dB, an IIP3 of -5 dBm, and a sensitivity of -77 dBm for the Bluetooth mode when the losses from the external components are compensated. It consumes 42 mA in receive ${\pi}/4-diffrential$ quadrature phase-shift keying $({\pi}/4-DQPSK)$ mode of 8 Mb/s, 35 mA in receive GFSK mode of 1 Mb/s, and 32 mA in transmit mode from a 2.5-V supply. These results indicate that the architecture and circuits are adaptable to the implementation of a low-cost, multi-mode, high-speed wireless personal area network.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2005년도 추계종합학술대회
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• pp.769-772
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• 2005

This paper describes a low-voltage and low-power channel selection analog front end with continuous-time low pass filters and highly linear programmable-gain amplifier(PGA). The filters were realized as balanced Gm-C biquadratic filters to achieve a low current consumption. High linearity and a constant wide bandwidth are achieved by using a new transconductance(Gm) cell. The PGA has a voltage gain varying from 0 to 65dB, while maintaining a constant bandwidth. A filter tuning circuit that requires an accurate time base but no external components is presented. With a 1-Vrms differential input and output, the filter achieves -85dB THD and a 78dB signal-to-noise ratio. Both the filter and PGA were implemented in a 0.18um 1P6M n-well CMOS process. They consume 3.2mW from a 1.8V power supply and occupy an area of $0.19mm^2$.

• Journal of electromagnetic engineering and science
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• 제14권2호
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• pp.61-67
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• 2014

This paper presents a zero-IF CMOS RF receiver, which supports three channel bandwidths of 5/10/40MHz for LTE-Advanced systems. The receiver operates at IMT-band of 2,500 to 2,690MHz. The simulated noise figure of the overall receiver is 1.6 dB at 7MHz (7.5 dB at 7.5 kHz). The receiver is composed of two parts: an RF front-end and a baseband circuit. In the RF front-end, a RF input signal is amplified by a low noise amplifier and $G_m$ with configurable gain steps (41/35/29/23 dB) with optimized noise and linearity performances for a wide dynamic range. The proposed baseband circuit provides a -1 dB cutoff frequency of up to 40MHz using a proposed wideband OP-amp, which has a phase margin of $77^{\circ}$ and an unit-gain bandwidth of 2.04 GHz. The proposed zero-IF CMOS RF receiver has been implemented in $0.13-{\mu}m$ CMOS technology and consumes 116 (for high gain mode)/106 (for low gain mode) mA from a 1.2 V supply voltage. The measurement of a fabricated chip for a 10-MHz 3G LTE input signal with 16-QAM shows more than 8.3 dB of minimum signal-to-noise ratio, while receiving the input channel power from -88 to -12 dBm.

• 한국가정과교육학회지
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• 제4권1호
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• pp.43-55
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• 1992

The purpose of this reasearch is to supply the basic data to improve Home Economics curriculum. This research was intended for 190 home economics teachers who are teaching in Kwang-Ju and chun-nam. The results are summarized as follows； 1. Among the objects of Home economics, the most important objects were to make students understand the significance of family life and development of family numbers. It requires 4 or 5 hours a week to learn these objects. 2. The amount of curriculum was immense and the level of curriculum was higher than students’level. More intencifying field are in this order； sex education, propriety education, consumption life, occupation, and computer education. 3. In home economics curriculum, the main stress was laid upon the application of action and learning content was focused on the matter set in the examination. 4. Theory and practical training classes were usually in the ratio of 7：3 and 8：2 in the current school classes. Ideal training classes are in the ration of 4：6, 5：5, 6：4, which showed that much weight was given to the practical exercises. 5. In practing subject matter, students tended to practice only main subject matter. The reason was primarily due to the lacks of equipments and faccilities, the limitation of training time for enterance examination and budgetary deficit. 6. Application of resorces was in the order of files, realia, samples, hanging chart, O.H.P and V.T.R. 7. The method of evaluation was mostly composed of paper and pens and practical evaluation when the practical evaluation was carrient out, in the case of necessity the standard of evaluation was made out.

• Asian-Australasian Journal of Animal Sciences
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• 제10권1호
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• pp.106-113
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• 1997

A field experiment was carried out on a dryland farming area of southern Bali for 92 weeks, to study the growth and fodder yield of 16 provenances of Gliricidia sepium in guardrow system. The experimental design was completely randomized blocks of 16 treatments (Gliricidia sepium provenances) replicated 3 times, with 6 plants per provenance. Six provenances were from Mexico (M), four from Guatemala (G), and one each from Colombia (C), indonesia (I), Nicaragua (N), Panama (P), Costa Rica (R) and Venezuela (V). After 40 weeks establishment the gliricidia were lopped 4 times a year at 150 cm height, at 2 months intervals during the 4 month wet season and 4 month intervals during the 8 month dry season. Stem elongation varied from 21 to 81 cm, leaf retention from 39 to 240%, branch number from 12 to 35, fodder yield from 1,090 to 3,153 g DW/plant. and wood yield from 743 to 2,750 g DW/plant. Pontezuelo provenance of Colombia (C24), Belen provenance of Nicaragua (N14) and Retalhuleu provenance of Guatemala (G14) were ranked first, second and third, respectively, for stem elongation, leaf retention, fodder and wood yields, during the wet and dry seasons.

• 한국의류학회지
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• 제39권2호
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• pp.247-256
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• 2015

This study prepared fabric-heating elements of carbon nanofiber composite to characterize morphologies and electrical properties. Carbon nanofiber composite was prepared with 15wt% PVDF-HFP/acetone solution, and 0, 1, 2, 4, 8, and 16wt% carbon nanofiber. Dispersion of solution was conducted with stirring for a week, sonification for 24 hours, and storage for a month, until coating. Carbon nanofiber composite coated fabrics were prepared by knife-edge coating on nylon fabrics with a thickness of 0.1mm. The morphologies of carbon nanofiber composite coated fabrics were measured by FE-SEM. Surface resistance was determined by KS K0555 and worksurface tester. A heating-pad clamping device connected to a variable AC/DC power supply was used for the electric heating characteristics of the samples and multi-layer fabrics. An infrared camera applied voltages to samples while maintaining a certain distance from fabric surfaces. The results of morphologies indicated that the CNF content increased specifically to the visibility and presence of carbon nanofiber. The surface resistance test results revealed that an increased CNF content improved the performance of coated fabrics. The results of electric heating properties, surface temperatures and current of 16wt% carbon nanofiber composite coated fabrics were $80^{\circ}C$ and 0.35A in the application of a 20V current. Carbon nanofiber composite coated fabrics have excellent electrical characteristics as fabric-heating elements.