• Journal of the Korea Academia-Industrial cooperation Society
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• v.9 no.2
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• pp.462-469
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• 2008

In this paper, we design the FPGA (Field-Programmable Gate Array) of the KOINONIA WPAN (Wireless Personal Area Network), and implement the SoC (System on Chip). We use the redundant bits to make a constant-amplitude in a modulator part. Additionally, the SNR (Signal to Noise Ratio) performance of the demodulator is improved by using the redundant bits in decoding steps. The four-million FPGA of the KOINONIA WPAN can be operated at 44MHz frequency. The PER (Packet Error Rate) of the designed FPGA with RF (Radio Frequency) module is below 1% at the -86dB MIPLS (Minimum Input Power Level Sensitivity), and the SNR is about 13dB. The SoC is implemented by using Hynix 0.25um CMOS (Complementary Metal Oxide Semiconductor) process. The size of the SoC is $6.52mm{\times}6.92mm$.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.6
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• pp.608-618
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• 2004

In this paper, modifying the diode star double balanced mixer of Maas, a novel resistive 60 GHz pHEMT MMIC star mixer is suggested. Due to star configuration, troublesome IF balun for ring configuration FET mixer is not necessary. In addition, the sysematic design method of dual balun through EM simulation is suggested rather than the design by inspection as Maas. The mixer circuit is fabricated as MMIC on CPW base using 0.1 um GaAs pHEMT Library of MINT in Dongguk University. The size is 1.5 ${\times}$ 1.5 $\textrm{mm}^2$ and its performance is adjustable by DC supply. It can be operated as both up and down converters and it shows the conversion loss of about 13∼18 ㏈ over the full V-band frequencies.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.12
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• pp.31-36
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• 2011

This paper investigates the ESD robustness of the stacked output driver with a 0.13um CMOS process. To represent an actual I/O system, we implemented stacked output driver circuits with pre-drivers and a rail-based power clamp. We implemented eight kinds of circuits varying pre-driver input connections and stacked driver size. The test circuits are examined with TLP measurements. It is shown that breakdown current and voltage can be increased by connecting the pre-driver input to a power supply and using stacked devices of a similar size. Based on the test results, design guideline is suggested to improve ESD robustness of the stacked output drivers.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.12
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• pp.37-44
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• 2011

This paper presents the method of improving the data rate and BER in the inductive coupling link using a BPM signaling method. A complementary switching transmitter is used to remove invalid glitches at transmitted data, and the concept of pre-distortion is introduced to optimize received data. Also, an integrating receiver is used to increase the sampling margin and equalizing transistors are added in the pre-charge path of the integrator and comparator for high frequency operation. The transceiver designed with a 0.13 um CMOS technology operates at 2.4 Gb/s and consumes 5.99 mW from 1.2 V power supply.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.1
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• pp.32-37
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• 2007

A DMB CMOS power amplifier (PA) with high efficiency and linearity is present. For this work, a 0.13-um standard CMOS process is employed and all components of the proposed PA are fully integrated into one chop including output matching network and adaptive bias control circuit. To improve the efficiency and linearity simultaneously, an adaptive bias control circuit is adopted along with second harmonic termination circuit at the drain node. The PA is shown a $P_{1dB}$ of 16.64 dBm, power added efficiency (PAE) of 38.31 %, and power gain of 24.64 dB, respectively. The third-order intermodulation (IMD3) and the fifth-order intermodulation (IMD5) have been -24.122 dBc and -37.156 dBc, respectively.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.11
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• pp.64-69
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• 2013

In this paper, a high-speed CMOS Image Sensor (CIS) based on a 10-bit two-step single-slope A/D converter is proposed. The A/D converter is composed of both a 5-bit coarse ADC and a 6-bit fine ADC, and the conversion speed is 10 times faster than that of the single-slope A/D converter. In order to have a small noise characteristics, further, a Digital Correlated Double Sampling(D-CDS) is also discussed. The proposed A/D converter has been fabricated with 0.13um 1-poly 4-metal CIS process, and it has a QVGA($320{\times}240$) resolution. The fabricated chip size is $5mm{\times}3mm$, and the power consumption is about 35mW at 3.3V supply voltage. The measured conversion speed is 10us, and the frame rate is 220 frames/s.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.10A
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• pp.809-815
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• 2011

In this paper, we have proposed and implemented a novel architecture which can be used to effectively design the modified Euclidean (ME) algorithm for key equation solver (KES) block in high-speed Reed-Solomon (RS) decoder. With polynomial expressions of newly-defined state variables for controlling each processing element (PE), the proposed architecture has simple input/output signals and requires less hardware complexity because no degree computation circuits are needed. In addition, since each PE circuit is independent of the error correcting capability t of RS codes, it has the advantage of linearly increase of the hardware complexity of KES block as t increases. For comparisons, KES block for RS(255,239,8) decoder is implemented using Verilog HDL and synthesized with 0.13um CMOS cell library. From the results, we can see that the proposed architecture can be used for a high-speed RS decoder with less gate count.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38A no.4
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• pp.303-309
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• 2013

A low power 6-bit flash ADC that uses an input voltage range detection algorithm is described. An input voltage level detector circuit has been designed to overcome the disadvantages of the flash ADC which consume most of the dynamic power dissipation due to comparators array. In this work, four digital input voltage range detectors are employed and each input voltage range detector generates the specific clock signal only if the input voltage falls between two adjacent reference voltages applied to the detector. The specific clock signal generated by the detector is applied to turn the corresponding latched comparators on and the rest of the comparators off. This ADC consumes 68.82mW with a single power supply of 1.2V and achieves 4.9 effective number of bits for input frequency up to 1MHz at 500 MS/s. Therefore it results in 4.75pJ/step of Figure of Merit (FoM). The chip is fabricated in 0.13-um CMOS process.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.12
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• pp.2569-2578
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• 2009

Core-A microprocessor is the all-Korean product designed as 32-bit embedded RISC microprocessor developed by KAIST and supported by the Industrial Property Office. This paper analyze Core-A microprocessor architecture and proposes efficient method to interface Core-A microprocessor with coprocessor. To verify proposed interfacing method, the AES cryptography processor that has 128-bit key and block size is used as a coprocessor. Coprocessor and AES are written in Verilog-HDL and verified using Modelsim simulator. It except AES module consists of about 3,743 gates and its maximum operating frequency is about 90Mhz under 0.35um CMOS technology. The proposed coprocessor interface architecture is efficiency to send data or to receive data from Core-A to coprocessor.

• Journal of IKEEE
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• v.25 no.2
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• pp.376-380
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• 2021

In this paper, we propose a novel ESD protection device with Latch-up immunity properties due to high holding voltages by improving the structure of a typical SCR. To verify the characteristics of the proposed ESD circuit, simulations were conducted using Synopsys TCAD and presented compared to existing ESD protection circuits. Furthermore, the variation of electrical properties was verified using the design variable D1. Simulation results confirm that the proposed ESD protective circuit has higher holding voltage properties and bidirectional discharge properties compared to conventional ESD protective circuits. We validate the electrical properties with post-design TLP measurements using Samsung's 0.13um BCD process. And we verify that the proposed ESD protection circuit in this paper is well suited for high voltage applications in that it has a latch-up immunity due to improved holding voltage through optimization of design variables.