• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 2001.05a
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• pp.215-218
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• 2001

최근 지능 정보 처리에 대한 연구가 여러 분야에서 활발히 진행되고 있으며, 불확실하고 복잡한 동적 환경에 적응할 수 있는 계산 모델로 점차 영역을 확장해 가고 있다. 따라서, 본 논문에서는 다치 논리함수의 차분의 성질을 이용한 다치 오토마타 모델을 제시한다. 즉, 입력 스트링 상태를 다치 함수의 치에 사상시키고, 다치 함수의 차분의 성질을 이용하여 상태의 전이에 적용시켜 동적 변화에 자율적으로 적응할 수 있도록 하였다. 그러므로 다치 오토마타는 동적으로 변화하는 시스템을 모델링 하는데 광범위하게 응용될 수 있을 것이다.

• Journal of the Korean Institute of Intelligent Systems
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• v.11 no.8
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• pp.701-708
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• 2001

Recently, the research on intelligence of computer has actively been under way in various areas and gradually extended to adapt to uncertain and complex environments. In this paper, we propose the MVL-Neural Valued Logic. Also, we verify that the MVL-Automata can be implemented to Neural Network and the MVL-Neural Network Model can be a simulator by MVL-Automata. Therefore, we propose that the MVL-Neural Network Model can be widely used in such area, as intelligent system or modeling of brain. In particular, the MVL-Neural Network is expected to be used as core technology of next generation computer.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 1997.10a
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• pp.275-279
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• 1997

최근 인공지능연구에서는 기호즈의와 커넥션니즘이 독립적으로 연구되어 왔으나 차츰 융합의 필요성이 절실히 요구되고 있다. 본 연구에서는 먼저 기호주의의 일부분인 고전논리를 확장한 다치논리와 커넥션니즘의 기본부분인 신경회로망을 융합한 다치신경망을 구성하고, BP에 기반을 둔 학습 MVL 네트워크를 이용하여 해석한다. 본 논문에서는 이러한 구성 및 해석방법을 확장하여 비고전적인 다치신경회로망을 구성하는 방법을 제안한다.

• Journal of the Korean Institute of Intelligent Systems
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• v.11 no.4
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• pp.311-314
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• 2001

Recently, research on Intelligent Information Process has actively been under way JD various areas and gradually extended to be adaptive to uncertain and complex dynamic environments. This paper presents a Multiple Valued Logic Automata(MVL-Automata) Model, utilizing properties of difference in a Multiple Valued Logic function. That is, MVL-Automata is able to be autonomously adapted to dynamic changing since an input stling is mapped to the value of a Multiple Valued Logic function and the property of difference in a Multiple Valued Logic function is applied to state transition. Therefore, Multiple Valued Logic Automata can be widely applied to the modeling dynamically of changing environments.

• Korean Journal of Logic
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• v.3
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• pp.27-51
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• 2000

이글의 기본적인 목적은 2치를 포함한 다치 논리 체계들간의 관계를 검토하는 데 있다. 이를 위하여 여기서는 명제를 대상으로 한 형식 의미 해석체계들 간에 고러해야 할 의미론적 확장 개념을 분명히 하였다. 구체적으로 다음의 두 작업이 수행되었다 첫째로 2치와 다치 논리 또는 다치 논리들간에 적용될 만한 의미론적 확장 개념을 의미해석의 바탕을 이루는 진리치 함수와 진리연산에 맞게 정의하였다. 둘째로 정의의 적합성을 확장, 비확장 사례 증명을 통해 예증해 보였다.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 2002.12a
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• pp.493-496
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• 2002

감정은 상당히 애매 모호하고 불명확하며 상대방의 감정을 이해하는 것은 매우 어렵다. 본 논문에서는 Plutchik의 감정 모델을 기호 다치 논리 함수의 미분을 이용하여 감정의 변화과정을 추론하는 방법을 제안한다.

• Journal of the Korean Institute of Intelligent Systems
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• v.12 no.2
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• pp.135-143
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• 2002

In this study, Multi-Values Logic processor was designed using the basic circuit of the electric current mode CMOS. First of all, binary FFT(Fast courier Transform) was extended and high-speed Multi-Valued Logic processor was constructed using a multi valued logic circuit. Compared with the existing two-valued FFT, the FFT operation can reduce the number of transistors significantly and show the simplicity of the circuit. Moreover, for the construction of amount was used inside the FFT circuit with the set of redundant numbers like {0, 1, 2, 3}. As a result, the defects in lines were reduced and it turned out to be effective in the aspect of normality an regularity when it was used designing VLSI(Very Large Scale Integration). To multiply FFT, the time and size of the operation was used toed as LUT(Lood Up Table).

• 전기산업
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• v.7 no.2
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• pp.110-113
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• 1996

• NEWSLETTER 전기공업
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• no.98-18 s.211
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• pp.24-40
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• 1998

• Journal of the Korea Computer Industry Society
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• v.3 no.1
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• pp.57-66
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• 2002

In this study, Multi-Values Logic processor was designed using the basic circuit of the electric current mode CMOS. First of all, binary FFT(Fast Fourier Transform) was extended and high-speed Multi-Valued Logic processor was constructed using a multi-valued logic circuit. Compared with the existing two-valued FFT, the FFT operation can reduce the number of transistors significantly and show the simplicity of the circuit. Moreover, for the construction of amount was used inside the FFT circuit with the set of redundant numbers like ［0,1,2,3］. As a result, the defects in lines were reduced and it turned out to be effective in the aspect of normality an regularity when it was used designing VLSI(Very Large Scale Integration). To multiply FFT, the time and size of the operation was used as LUT(Look Up Table) Finally, for the compatibility with the binary system, multiple-valued hybrid-type FFT processor was proposed and designed using binary-four valued encoder, four-binary valued decoder, and the electric current mode CMOS circuit.