• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1205-1208
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• 2003

본 논문에서는 분할된 스캔을 이용한 저전력 BIST 구조를 제안한다. 제안하는 BIST는 내부 스캔 패스를 회로의 구조적인 정보와 테스트 패턴 집합의 특성에 따라 4개의 스캔 패스로 분할하고 일부 스캔 패스에만 입력패턴이 인가되도록 설계하였다. 따라서 테스트 패턴 입력 시에 스캔 패스로의 쉬프트 동작 수를 줄임으로써 회로 내부의 전체 상태천이 수를 줄일 수 있다. 또한 4개로 분할되는 스캔패스의 길이를 고려하여 각 스캔 패스에 대해 1/4의 속도로 낮춰진 테스트 클럭을 인가함으로써 전체 회로의 전력 소모를 줄일 수 있도록 하였다. ISCAS89 벤치마크 회로에 대한 실험을 통하여 제안하는 BIST 구조가 기존 BIST 구조에 비해 최대 21%까지 전력소모를 줄일 수 있음을 확인하였다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.2
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• pp.65-77
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• 2000

We propose a new formulation by quadratic boolean programming to partition circuits for FPGA based reconfigurable circuit boards, in which the routing topology among IC chips are predetermined. The formulation is to minimize the sum of the wire length by considering the nets passing through IC chips for the interconnections between chips which are not adjacent, in addition to the constraints considered by the previous partition methods. We also describe a heuristic method, which consist of module assignment method to efficiently solve the problem. Experimental results show that our method generates the partitions in which the given constraints are all satisfied for all the benchmark circuits tested. The pin utilization are reduced for the most of the circuits and the total wire length of the routed nets are improved up to 34.7% compared to the previous method.

• The Journal of the Korea Contents Association
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• v.21 no.7
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• pp.164-170
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• 2021

In VLSI design, partitioning is a task of clustering objects into groups so that a given objective circuit is optimized. It is used at the layout level to find strongly connected components that can be placed together in order to minimize the layout area and propagation delay. The most popular algorithms for partitioning include the Kernighan-Lin algorithm, Fiduccia-Mattheyses heuristic and simulated annealing. In this paper, we propose a adapted genetic algorithm searching solution space for the circuit partitioning problem, and then compare it with simulated annealing and genetic algorithm by analyzing the results of implementation. As a result, it was found that an adaptive genetic algorithm approaches the optimal solution more effectively than the simulated annealing and genetic algorithm.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.8 no.5
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• pp.1076-1081
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• 2007

In this paper, we propose a new switch structure for time division duplex(TDD) system. The existing TDD structure utilizes a circulator fur isolation characteristic between ports. However, the circulator produces intermodulation distortion signals which are undesired signal because of its nonlinear properties. The proposed circuit is composed of a modified branch-line hybrid coupler which controls the signal flow while the isolated port is open-/short- terminated. In order to prove the validity of the presented structure, the switch circuit is fabricated and measured at 2.3GHz, the center frequency of Wibro service system.

• Journal of the Korea Society for Simulation
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• v.5 no.2
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• pp.73-84
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• 1996

As circuits are larger and more complicated, logic simulation is playing a very important role in design verification. A good simulator should be fast and accurate, but unknown values in 3 value simulator may generate X-propagation problem which makes inaccurate output values. In this paper, a new partitioning method is devised to deal with X-propagation problem efficiently and an efficient algorithm is developed which is able to optimize time and accuracy by controlling partition depths. The results prove the effectiveness of the new simulation algorithm using some benchmark circuits.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.05a
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• pp.795-797
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• 2013

This paper describes a charge sharing capacitive-sensing circuit technique that improves the quality of images captured with fingerprint sensor LSIs. When the finger is dry, the electrical resistance of a finger surface is high. It leads to poor image quality. To capture clear images even when the finger is dry, the modified capacitive detection circuit improves the image quality using an enhancement plate at the finger surface and a voltage control circuit. The test circuit is analyzed on $0.35{\mu}m$ CMOS process.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.9
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• pp.21-28
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• 1998

In this paper, we propose an efficient linear ordering algorithm, called LIME, for netlist partitioning. LIME incrementally merges two segments which are selected based on the proposed cost function until only one segment remains. The final resultant segment then corresponds to the linear ordering. LIME also runs extremely fast, because it exploits sparsity of netlist. Compared to the earlier work, the proposed algorithm is eight times faster in producing linear ordering and yields an average of 17% improvement for the multi-way scaled cost partitioning.

• Proceedings of the KIPE Conference
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• 2019.11a
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• pp.152-153
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• 2019

본 논문에서는 캐패시터-분할 타입 능동전력 디커플링 회로를 위한 전압제어 방법을 제안한다. 능동전력 디커플링 회로는 시스템에 필요한 커패시턴스를 낮추어 전해커패시터를 필름 커패시터로 대체하여 시스템 수명과 전력밀도를 높일 수 있는 장점이 있다. 그러나 일반적으로 오픈 루프 제어방식의 전압제어 방식을 사용하여 파라미터 값의 변화에 민감하다는 단점을 가지고 있다. 이에 본 논문에서는 커패시터-분할 타입 능동전력 디커플링 회로를 위한 폐루프 제어 방법을 제안한다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.12 no.3
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• pp.267-275
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• 1987

This paper concerns a study on the theory of tearing which analyzes a large scale network by partitioning it into a number of small subnetworks by cutting through some of the existing nodes and branches in the network. By considering of the relationship its voltage and current of node cutting before and after, the consititutive equations of tearing method is equvalent to renumbering the nodes of untorn network equations. Therefore the analysis of network is conveniently applied as same algorithm that is used in untorn network. Also the proposed nodal admittnace matrix is put in block diagonal form, therefore this method permit parallel processing analysis of subnetworks. 30 nodes network was tested and the effectiveness of the proposed algorithm was proved.

• Journal of KIISE:Computer Systems and Theory
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• v.29 no.7
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• pp.422-430
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• 2002

For a time-multiplexed FPGA, a circuit is partitioned into several subcircuits, so that they temporally share the same physical FPGA device by hardware reconfiguration. In these architectures, all the hardware reconfiguration information called contexts are generated and downloaded into the chip, and then the pre-scheduled context switches occur properly and timely. Since the maximum number of the LUT's required in the same time determines the size of the chip used in the synthesis, it needs to be minimized, if possible. Many previous work use their own approaches, which are very similar to either scheduling method in high level synthesis or multi-way circuit partitioning method, to solve the problem. In this paper, we propose a method which estimates the lower bound on the number of LUT's without performing any actual synthesis. The estimated lower bounds help to evaluate the results of the previous work. If the estimated lower bound on the number of LUT's exactly matches the number of LUT's of the result from the previous work, the result must be optimal. In contrast, if they do not match, the following two cases are expected : the more exact lower bound may exist, or we might find the new synthesis result better than the result from the previous work. Experimental results show that our lower bound estimation method is very accurate. In almost al] cases experimented, the estimated lower bounds on the number of LUT's exactly match those of the previous synthesis results respectively, implying that the best results from the previous work are optimal as well as our method predicted the exact lower bound for those examples.