• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.433-434
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• 2008

반도체 공정 기술의 진보로 인해 InP/InGaAs로 제작된 애벌랜치 포토다이오드가 고속 광통신 시스템에서 사용되고 있다. 하지만 경계 항복에 의한 접합 부분의 강한 전기장으로 인한 문제와 항복 이득의 저하 문제로 소자 특성의 문제가 발생하고 있다. 이 논문에서는 소자 구조 변화에 따른 고속 InP/InGaAs 애벌랜치 포토다이오드의 특성 변화를 공정/소자 시뮬레이션을 이용하여 분석하였다.

• Proceedings of the Korean Vacuum Society Conference
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• 2009.08a
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• pp.164-164
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• 2009

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.9
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• pp.1771-1777
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• 2016

In this thesis, the breakdown voltage characteristics of silicon nanowire N-channel GAA MOSFETs were analyzed through experiments and 3-dimensional device simulation. GAA MOSFETs with the gate length of 250nm, the gate dielectrics thickness of 6nm and the channel width ranged from 400nm to 3.2um were used. The breakdown voltage was decreased with increasing gate voltage but it was increased at high gate voltage. The decrease of breakdown voltage with increasing channel width is believed due to the increased current gain of parasitic transistor, which was resulted from the increased potential in channel center through floating body effects. When the positive charge was trapped into the gate dielectrics after gate stress, the breakdown voltage was decreased due to the increased potential in channel center. When the negative charge was trapped into the gate dielectrics after gate stress, the breakdown voltage was increased due to the decreased potential in channel center. We confirmed that the measurement results were agreed with the device simulation results.

• Journal of IKEEE
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• v.15 no.1
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• pp.37-42
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• 2011

In this paper, the high-voltage novel devices have been fabricated by 0.35 um BCD (Bipolar-CMOS-DMOS) process. Electrical characteristics of 20 V level BJT device, 30/60 V HV-CMOS, and 40/60 V LDMOS are analyzed. Also, the vertical/lateral BJT with the high-current gain and LIGBT with the high-voltage are proposed. In the experimental results, vertical/lateral BJT has breakdown voltage of 15 V and current gain of 100. The proposed LIGBT with the high-voltage has breakdown voltage of 195 V, threshold voltage of 1.5 V, and Vce, sat of 1.65 V.

• Journal of IKEEE
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• v.23 no.3
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• pp.832-838
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• 2019

In this paper, 4H-SiC MOSFET, the next generation power semiconductor device, was studied. In particular, Semi-SJ MOSFET structures with improved electrical characteristics than conventional DMOSFET structures were proposed in the class of 3300V, and static characteristics of conventional and proposed structures were compared and analyzed through TCAD simulations. Semi-SuperJunction MOSFET structure is partly structure that introduces SuperJunction, improves Electric field distribution through the two-dimensional depletion effect, and increases breakdown voltage. Benefit from the improvement of breakdown voltage, which can improve the on resistance as high doping is possible. The proposed structure has a slight reduction in breakdown voltage, but has an 80% decrease in on resistance compared to the conventional DMOSFET structure, and a 44% decrease in on resistance compared to the Current Spreading Layer(CSL) structure that improves the conventional DMOSFET structure.

• Journal of the Korean Vacuum Society
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• v.14 no.1
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• pp.29-34
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• 2005

The degradation of the SiGe hetero-junction bipolar transistor(HBT) properties in SiGe BiCMOS process was investigated in this paper. The SiGe HBT prepaired by SiGe BiCMOS process, unlike the conventional one, showed the degraded DC characteristics such as the decreased Early voltage, the decreased collector-emitter breakdown voltage, and the highly increased base leakage current. Also, the cutoff frequency(f/sub T/) and the maximum oscillation frequency(f/sub max/) representing the AC characteristics are reduced to below 50%. These deteriorations are originated from the change of the locations of emitter-base and collector-base junctions, which is induced by the variation of the doping profile of boron in the SiGe base due to the high-temperature source-drain annealing. In the result, the junctions pushed out of SiGe region caused the parastic barrier formation and the current gain decrease on the SiGe HBT device.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.28 no.5
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• pp.430-433
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• 2017

This paper presents a S/C/X-band LNA MMIC with resistive feedback structure in 0.25 um GaN HEMT process. The GaN devices have advantages as a high output power device having high breakdown voltage, energy band gap and stability at high temperature. Since the receiver using the GaN device with high linearity can be implemented without a limiter, the noise figure of the receiver can be improved and the size of receiver module can be reduced. The proposed GaN LNA MMIC based on 0.25 um GaN HEMT device is achieved the gain of > 15 dB, the noise figure of < 3 dB, the input return loss of > 13 dB, and the output return loss of > 8 dB in the S/C/X-band. The current consumption of GaN LNA MMIC is 70 mA with the drain voltage 20 V and the gate voltage -3 V.

• Journal of Sensor Science and Technology
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• v.3 no.3
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• pp.16-21
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• 1994

A 3-terminal pin-type photosensor with gate contrail is fabricated using standard silicon CMOS IC process. The photosensor of a $100{\mu}m{\times}120{\mu}m$ size has dark current less than 1nA and its breakdown voltage is -14V with a depletion capacitance 0.75 pF at -5V reverse bias. Responsivity at 0V gate voltage is 0.25A/W at $0.633{\mu}m$ wavelength, 0.19A/W at $0.805{\mu}m$. Responsivity increases with increasing gate voltage. The integrated circuit of photosensor and CMOS inverter shows $22K{\Omega}$ transimpedance and photocurrent of $90{\mu}A$ switchs the output state of digital inverter without additional amplifier.