• The KIPS Transactions:PartA
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• v.11A no.1
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• pp.1-10
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• 2004

A cellular array parallel multiplier with parallel-inputs and parallel-outputs for performing the multiplication of two polynomials in the finite fields GF$(2^m)$ is presented in this paper. The presented cellular way parallel multiplier consists of three operation parts: the multiplicative operation part (MULOP), the irreducible polynomial operation part (IPOP), and the modular operation part (MODOP). The MULOP and the MODOP are composed if the basic cells which are designed with AND Bates and XOR Bates. The IPOP is constructed by XOR gates and D flip-flops. This multiplier is simulated by clock period l${\mu}\textrm{s}$ using PSpice. The proposed multiplier is designed by 24 AND gates, 32 XOR gates and 4 D flip-flops when degree m is 4. In case of using AOP irreducible polynomial, this multiplier requires 24 AND gates and XOR fates respectively. and not use D flip-flop. The operating time of MULOP in the presented multiplier requires one unit time(clock time), and the operating time of MODOP using IPOP requires m unit times(clock times). Therefore total operating time is m+1 unit times(clock times). The cellular array parallel multiplier is simple and regular for the wire routing and have the properties of concurrency and modularity. Also, it is expansible for the multiplication of two polynomials in the finite fields with very large m.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.4
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• pp.11-20
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• 1998

Fault simulatior has been used to compute exact fault coverages of test vectors for digial circuits. But it is time consuming because execution time is proportional to square of circuit size. Recently, several algorithms for testability analysis have been published to cope with these problems. COP is very fast and accurate but cannot be used for sequential circuits, while STAFAN can be used for sequential circuits but needs vast amount of execution time due to good circuit simulation. We proposed EXTASEC which gave fast and accurate fault coverage. But it shows noticeable errors for a few sequential circuits. In this paper, it is shown that the inaccuracy is due to uninitializble flipflops, and we propose ITEM to improve the EXTASEC algorithm. ITEM is an improved evaluation method of fault coverage by analysis of backward lines and uninitializable flipflops. It is expected to perform efficiently for very large circuits where execution time is critical.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.7
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• pp.75-81
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• 1993

In this paper, New type of Static Edge Triggered D Flip-Flop Circuits which are effective for the sequencial selecting and addressing of Matrix type Electrodes being applied to Flat Display Devices is proposed by the Design Technique using the Transmission Characteristics of Feedback Transistors and Charge Back Up Function. These Circuits composed of 2-4 less transistors in number than Conventional Static D Flip Flop's have some advantages that the Maximum Transition Time of Clock Signals allowed is increased by 100-450 times more than that of the Conventional circuit at 100KHz Clock Frequence and Circuit Safety is much increased by making the wider ranges, 1-4V, of Clock Levelas a Non-operating periods than 3-3.2V ranges in case of the Conventional Circuit at 10MHz clock frequence. By these advantages, These circuits can be very effectively used in case that clock signal has long transition time, especially on the low frequency operation.

• Journal of the Korean Institute of Intelligent Systems
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• v.10 no.5
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• pp.478-486
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• 2000

This paper proposes a design method that can minimize the power dissipation of CMOS digital circuits without affecting their optimal operation speeds. The proposed method is based on genetic algorithms(GAs) combined to the retiming technique, a circuit transformation technique of repositioning flip-flops. The proposed design method consists of two phases: the phase of retiming for optimizing clock periods and the phase of GA retiming for minimizing power dissipation. Experimental results using Synopsys Design Analyzer show that the proposed design method can reduce the critical path delay of example circuits by about 30-50% and improve the dynamic power performance of the circuits by about 1.4~18.4%.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.1
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• pp.10-14
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• 1998

In this paper a double edge triggered (DET) filp-flop is proposed which changes its output state at both the positive and the negative edge transitions of the triggering input. DET filp-flop has advantages in terms of speed and power dissipation over single edge triggered (SET) filp-flop has proposed DET flip-flop needs only 12 MOS transistors and can operate at clock speed of 500 MHz. Also, the power dissipation has decreased about 33% in comparison to SET flip-flop.

• Proceedings of the KIEE Conference
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• 1983.07a
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• pp.234-236
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• 1983

본 논문은 펄스형 순차회로(pulse mode sequential circuit)를 설계하는데 필요한 여러가지 복잡한 단계의 간소화를 목적으로 한, 컴퓨터를 이용한 회로 설계법을 제안하고자 한다. 여기서 제안된 방법에 의하면 여러 종류의 플립-플롭 (flip-flop)에 대한 회로의 설계를 반복 시행하고, 또 다출력 함수 최소화(multiple output function minimization) 방법을 적용함으로 해서 거의 적소에 가까운 비용으로 원하는 회로를 설계할 수 있다. 제안된 회로 설계법의 프로그램은 포트란(FORTRAN)으로 작성되었으며, 이에 의한 실에의 예와 그 결과를 종래 방법에 의한 것과 비교, 분석했다.

• The Transactions of the Korea Information Processing Society
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• v.3 no.5
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• pp.1346-1353
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• 1996

In this paper, we propose a modeling method for the flip-flops and test generation algorithms to detect the faults in the sequential circuits using VHDL in the high-level design environment. RS, JK, D and T flip-flops are modeled using data flow types. The sequence of micro-operation which is the basic structure of a chip-level leads to a control point where varnishing occurs to one of two micro- operation sequence. In order to model the fault of one micro-operation(FMOP) that perturb another micro-operation effectively, the concept of goal trees and some heuristic rules are used. Given a faulty FMOP or fault of control point (FCON), a test pattern is generated by fault sensitization, path sensitization and determination of the imput combinations that will justify the path sensitization. The fault models are restricted to the data flow model in the ARCHITECTURE statement of VHDL. The proposed algorithm is implemented in the C language and its efficiency is confirmed by some examples.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.7
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• pp.17-26
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• 2016

This work proposes a 12b 60MS/s 0.18um CMOS Flash-SAR ADC for various systems such as wireless communications and portable video processing systems. The proposed Flash-SAR ADC alleviates the weakness of a conventional SAR ADC that the operation speed proportionally increases with a resolution by deciding upper 4bits first with a high-speed flash ADC before deciding lower 9bits with a low-power SAR ADC. The proposed ADC removes a sampling-time mismatch by using the C-R DAC in the SAR ADC as the combined sampling network instead of a T/H circuit which restricts a high speed operation. An interpolation technique implemented in the flash ADC halves the required number of pre-amplifiers, while a switched-bias power reduction scheme minimizes the power consumption of the flash ADC during the SAR operation. The TSPC based D-flip flop in the SAR logic for high-speed operation reduces the propagation delay by 55% and the required number of transistors by half compared to the conventional static D-flip flop. The prototype ADC in a 0.18um CMOS demonstrates a measured DNL and INL within 1.33LSB and 1.90LSB, with a maximum SNDR and SFDR of 58.27dB and 69.29dB at 60MS/s, respectively. The ADC occupies an active die area of $0.54mm^2$ and consumes 5.4mW at a 1.8V supply.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.10
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• pp.96-106
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• 2014

Previous academic research on FPGA tools has relied on simple imaginary models for the targeting architecture. As the first step to overcome such restriction, the issues on analytic placement and legalization which are applied to commercial FPGAs have been brought up, and several techniques to remedy them are presented, and evaluated. First of all, the center of gravity of the placed cells may be far displaced from the center of the chip during analytic placement. A function is proposed to be added to the objective function for minimizing this displacement. And then, the density map is expanded into multiple layers to accurately calculate the density distribution for each of the cell types. Early fixation is also proposed for the memory blocks which can be placed at limited sites in small numbers. Since two flip-flops share control pins in a slice, a compatibility constraint is introduced during legalization. Pre-packing compatible flip-flops is proposed as a proactive step. The proposed techniques are implemented on the K-FPGA fabric evaluation framework in which commercial architectures can be precisely modeled, and modified for enhancement, and validated on twelve industrial strength examples. The placement results show that the proposed techniques have reduced the wire length by 22%, and the slice usage by 5% on average. This research is expected to be a development basis of the optimization CAD tools for new as well as the state-of-the-art FPGA architectures.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.8
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• pp.72-84
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• 2001

The timings of all computational elements in the micropipeline circuits are important. The previous researches on path delay testing using scan methods make little account of the characteristic of the path delay tests that the second test pattern must be more controllable. In this paper, a new scan latch is proposed which is suitable to path delay testing of the micropipelines and has small area overhead. Results show that path delay faults in the micropipeline circuits using the new scan are testable robustly and the fault coverage is higher than the previous researches. In addition, the new scan latch for path delay faults testing in the micropipeline circuits can be easily expanded to the applications such as BIST for stuck-at faults.