• Journal of Korea Multimedia Society
• /
• v.14 no.5
• /
• pp.669-680
• /
• 2011

R-trees are widely used in various areas such as geographical information systems, CAD systems and spatial databases in order to efficiently index multi-dimensional data. As data sets used in these areas grow in size and complexity, however, range query operations on R-tree are needed to be further faster to meet the area-specific constraints. To address this problem, there have been various research efforts to develop strategies for acceleration query processing on R-tree by using the buffer mechanism or parallelizing the query processing on R-tree through multiple disks and processors. As a part of the strategies, approaches which parallelize query processing on R-tree through Graphics Processor Units(GPUs) have been explored. The use of GPUs may guarantee improved performances resulting from faster calculations and reduced disk accesses but may cause additional overhead costs caused by high memory access latencies and low data exchange rate between GPUs and the CPU. In this paper, to address the overhead problems and to adapt GPUs efficiently, we propose a novel approach which uses a GPU as a buffer to parallelize query processing on R-tree. The use of buffer algorithm can give improved performance by reducing the number of disk access and maximizing coalesced memory access resulting in minimizing GPU memory access latencies. Through the extensive performance studies, we observed that the proposed approach achieved up to 5 times higher query performance than the original CPU-based R-trees.

• Journal of KIISE:Software and Applications
• /
• v.32 no.7
• /
• pp.683-692
• /
• 2005

Java specification states that all accesses to an object must be checked at runtime if object refers to null. Since Java is an object-oriented language, object accesses are frequent enough to make null pointer checks affect the performance significantly. In order to reduce the performance degradation, there have been attempts to remove redundant null pointer checks. For example, in a Java environment where a just-in-time (JIT) compiler is used, the JIT compiler removes redundant null pointer check code via code analysis. This paper proposes a technique to remove additional null pointer check code that could not be removed by previous JIT compilation techniques, via early null pointer check using an architectural feature called predication. Generally, null point check code consists of two instructions: a compare and a branch. Our idea is moving the compare instruction that is usually located just before an use of an object, to the point right after the object is defined so that the total number of compare instructions is reduced. This results in reduction of dynamic and static compare instructions by 3.21$\%$ and 1.98$\%$. respectively, in SPECjvm98 bechmarks, compared to the code that has already been optimized by previous null pointer check elimination techniques. Its performance impact on an Itanium machine is an improvement of 0.32$\%$.

• Journal of KIISE:Computer Systems and Theory
• /
• v.29 no.4
• /
• pp.232-243
• /
• 2002

There are many methods for improving TLB (translation lookaside buffer) performance, such as increasing the number of entry in TLB, supporting large page or multiple page sizes. The best way is to support multiple page sizes, but any operating system doesn't support multiple page sizes in user mode. So, we propose the new structure of TLB supporting two pages to obtain the effect of multiple page sizes with high performance and at low cost without operating system support. we propose a new TLB structure supporting two page sizes dynamically and selectively for high performance and low cost design without any operating system support. For high performance, a promotion-TLB is designed by supporting two page sizes. Also in order to attain low power consumption, a banked-TLB is constructed by dividing one fully associative TLB space into two sub-fully associative TLBs. These two banked-TLB structures are integrated into a banked-promotion TLB as a low power and high performance TLB structure for embedded processors. According to the results of comparison and analysis, a similar performance can be achieved by using fewer TLB entries and also power consumption can be reduced by around 50% comparing with the fully associative TLB.

• KIPS Transactions on Computer and Communication Systems
• /
• v.1 no.1
• /
• pp.1-10
• /
• 2012

The way-lookup cache and the way-tracking cache are considered to be the most energy-efficient when used for level 1 and level 2 caches, respectively. This paper proposes an energy-efficient set-associative cache using the bi-mode way-selector that combines the way selecting techniques of the way-tracking cache and the way-lookup cache. The simulation results using an Alpha 21264-based system show that the bi-mode way-selecting L1 instruction cache consumes 27.57% of the energy consumed by the conventional set-associative cache and that it is as energy-efficient as the way-lookup cache when used for L1 instruction cache. The bi-mode way-selecting L1 data cache consumes 28.42% of the energy consumed by the conventional set-associative cache, which means that it is more energy-efficient than the way-lookup cache by 15.54% when used for L1 data cache. The bi-mode way-selecting L2 cache consumes 15.41% of the energy consumed by the conventional set-associative cache, which means that it is more energy-efficient than the way-tracking cache by 16.16% when used for unified L2 cache. These results show that the proposed cache can provide the best level of energy-efficiency regardless of the cache level.

• The KIPS Transactions:PartA
• /
• v.15A no.6
• /
• pp.309-316
• /
• 2008

The mission-critical engagement control computer for air defense has to maintain its operation without any fault for a long mission time. The mission performed by large-scale and complex embedded software is extremely critical in terms of dependability and safety of computer system, and it is very important that engagement control computer has high reliability. The engagement control computer was implemented using four processors. The distributed computer composed of four processors quarantees the dependability and safety, and ASR fault-tolerant technique applied to each processor guarantees the reliability. In this paper, the mechanism and performance of ASR fault-tolerant technique are analysed. And MTBF, reliability, availability, and cost-effectiveness for ASR, DMR and TMR techniques applied to the engagement control computer are analysed. The mission-critical engagement control computer using software-based ASR fault-tolerant technique provides high reliability and fast recovery time at a low cost. The mission reliability of the engagement control computer using ASR technique in 4 processors board is almost same the reliability of the computer using TMR technique in 6 processors board. ASR technique is most suitable to the mission-critical engagement control computer.

• Proceedings of the Korea Water Resources Association Conference
• /
• 2016.05a
• /
• pp.74-74
• /
• 2016

복잡한 지형에서 컴퓨터를 이용한 물리적 기반 수치모의는 합리적인 시간내에 연산을 완료하기 위해 대개 큰 연산장비 들을 요구한다. 더욱이 모의되는 현상이 시간단계마다 갱신되어지는 동역학적 현상에 기반된 비정상상태일 때 연산성능은 고려되어지는 가장 중요한 주제가 될 수 있다. 연산 시간을 줄이기 위한 가장 널리 이용되는 전략중의 하나는 적절한 수의 프로세서를 이용하는 병렬 기법이다. 최근 들어 연산속도를 가속화하기 위해 다수의 코어를 이용한 OpenMP 와 MPI 기법들이 병렬해석기법으로 대두되었고 그래픽 연산장치를 이용한 병렬처리 해석기법도 소개되고 있다. 본 연구에서는 중앙연산장치를 이용한 병렬 해석기법을 이용하여 제내지 침수해석의 적용성을 검토하고 그 결과을 비교하였다. 본 연구를 위해 OpenMP 병렬기법을 이용하여 확산파 침수해석 프로그램의 원시코드를 재작성하여 가상 및 실제 유역에 적용하였다. 해석결과는 분산메모리 병렬해석 기법인 MPI를 도입한 모형의 결과와 비교되었다. OpenMP를 도입한 모형과 MPI를 도입한 경우 유량 및 수심의 경우 오차 허용 한계내에 수렴되어 만족되었으나 그러나 연산 속도의 경우 두 기법간의 자료의 저장 방법 차이로 인해 차이를 나타내었다. 가상 유역에 적용된 결과로 검토된 각 기법의 증속(speedup) 효과는 MPI의 경우 4 코어를 이용하였을 때 최고 2.62 배 정도에 도달하는 것으로 나타났다. OpenMP 를 적용한 경우 2.87 배 정도로 나타나 OpenMP 를 이용하였을 때 증속효과가 조금 더 뛰어났다. 이는 두 기법의 메모리 저장방식의 차이로 인해 자료의 전송량과 전송 시간이 적은 OpenMP 를 도입한 모형에서 MPI 모형 보다 상대적으로 뛰어난 결과를 나타내었다. 실제 유역의 적용을 위해 상대적으로 우수한 증속결과를 나타낸 OpenMP를 도입한 모형을 Malpasset 댐 붕괴 유역에 적용하였다. 적용된 요소의 수는 각각 45254, 11352 개로 비교적 많은 요소를 가진 하류지역에 적용하여 병렬효과를 극대화하고자 하였다. 적용결과 두 경우 모두 병렬 해석 기법을 도입한 모형에서 유속과 침수심 등은 순차적 모형과 동일한 값을 나타내었으나 증속효과로 인한 연산시간은 순차적 모형에서 8.57 배로 나타나 병렬 모형의 상대적으로 빠른 연산속도를 판단할 있었다. 위의 적용결과를 통해 계산 요소들이 많은 2 차원 해석의 경우 기존의 단일 코어를 이용한 순차적 해석은 장시간에 걸치 연산시간으로 인해 작업효율이 낮아지는 결과를 발생시킬 수 있으며 병렬 해석을 도입할 경우 주어진 컴퓨터 자원를 효율적으로 이용가능하여 합리적인 연산시간으로 연산결과를 얻는 것이 가능하여 반복적 통계 기법/Ensemble 해석 등을 이용한 종합적 해석이 좀 더 실용적으로 이루어 질 수 있을 것이라고 판단되었다.

• Journal of the Korea Society of Computer and Information
• /
• v.25 no.6
• /
• pp.9-15
• /
• 2020

In this paper, we propose a case that drone (unmanned aerial vehicle), one of the representative technologies of the 4th Industrial Revolution, threatens airport safety and privacy infringement, and describes a drone control system proposal to solve the problem. Unmanned aerial vehicle (Drone) is creating a serious problem recently, In Korea, on May 21, 19, according to the Jeju Regional Aviation Administration, drones flew over Jeju Jeongseok Airfield twice in the same month, causing problems in aircraft operation. In overseas cases, two drones near the runway of Gatwick International Airport in the UK There has been a disturbance in which the takeoff and landing of the aircraft flies for a while, and various problems have occurred, such as voyeuring the private life of an individual using a drone. This paper is equipped with an Acess Point transponder mounted on a drone (unmanned aerial vehicle), and unspecified many who want to receive flight information (coordinates, altitude, and obstacles) of the drone access the drone AP, receive and receive the flight information of the drone, and receive unspecified multiple Drone AP flight information is collected and collected to provide the information of the drone currently floating on one user interface screen. In addition, an AP transponder is proposed to operate a safe drone (unmanned aerial vehicle) and the drone's flight information is transmitted., To receive and collect and collect data.

• The Journal of Korean Institute of Information Technology
• /
• v.15 no.12
• /
• pp.157-164
• /
• 2017

Mobile ECG signal measurement is a technique to measure small signals of several mV, and many studies have been conducted to remove noise including wandering scheme. Removal of the equipotential line noise caused by shaking or movement of the electrode cable is one of the core research contents for the electrocardiogram measurement. In this study, we proposed a modified step-size of combined NLMS(normalized least squares) and DLMS(delayed least squares) adaptive filter to eliminate baseline noise from ECG signals. The proposed method mainly adjusts initial filter step-size to reduce distortion of original ECG signals characteristic after eliminating baseline noise. The modified filter step-size is scaled by filter order size and distortion minimization factor. This method is suitable for portable ECG device with a small processor and less power consumption. This technique also decreases computation time which is essential for real-time filtering. The proposed filter also increase the signal to noise ratio (SNR) compared to conventional NLMS filter.

• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.21 no.6
• /
• pp.49-55
• /
• 2021

Recently, a small tracking radar requires the development of a small millimeter wave tracking radar having a high range resolution that can acquire and track a target in various environments and disable the target system with a single blow. Small millimeter wave tracking radar with high range resolution needs to implement a signal processor that can process wide bandwidth signals in real time and meet the requirements of small tracking radar. In this paper, we designed a signal processor that can perform the role and function of a signal processor for a small millimeter wave tracking radar. The signal processor for the small millimeter wave tracking radar requires the real-time processing of input signal of OOOMHz center frequency and OOOMHz bandwidth from 8 channels. In order to satisfy the requirements of the signal processor, the signal processor was designed by applying the high-performance FPGA (Field Programmable Gate Array) and ADC (Analog-to-digital converter) for pre-processing operations, such as DDC (Digital Down Converter) and FFT (Fast Fourier Transform). Finally, the signal processor of the small millimeter wave tracking radar was verified via performance test.

• Journal of Internet Computing and Services
• /
• v.22 no.2
• /
• pp.59-68
• /
• 2021

As artificial intelligence(AI) technologies, which have made rapid growth recently, began to be applied to the marine environment such as ships, there have been active researches on the application of CNN-based models specialized for digital videos. In E-Navigation service, which is combined with various technologies to detect floating objects of clash risk to reduce human errors and prevent fires inside ships, real-time processing is of huge importance. More functions added, however, mean a need for high-performance processes, which raises prices and poses a cost burden on shipowners. This study thus set out to propose a method capable of processing information at a high rate while maintaining the accuracy by applying Quantization techniques of a deep learning model. First, videos were pre-processed fit for the detection of floating matters in the sea to ensure the efficient transmission of video data to the deep learning entry. Secondly, the quantization technique, one of lightweight techniques for a deep learning model, was applied to reduce the usage rate of memory and increase the processing speed. Finally, the proposed deep learning model to which video pre-processing and quantization were applied was applied to various embedded boards to measure its accuracy and processing speed and test its performance. The proposed method was able to reduce the usage of memory capacity four times and improve the processing speed about four to five times while maintaining the old accuracy of recognition.