• Proceedings of the Korea Institutes of Information Security and Cryptology Conference
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• 2002.11a
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• pp.334-337
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• 2002

특정 프로그램의 취약점 여부를 판단하기 위해 프로그램의 버전이나 작동여부를 점검하여 검증하는 방식이 많이 사용되었다. 하지만, 이 방식은 취약점 증명에 영향을 미치는 많은 요소들을 모두 고려할 수 없기 때문에 점검 결과가 부정확하다는 단점이 있다. 최근에는 이를 보완하기 위해 해당 프로그램에 실제로 공격을 수행하고 그 성공 여부를 통해 취약점 여부를 검증하는 방식이 사용되고 있다. 이렇게 실제 공격코드를 이용하는 방법은 정확한 결과를 얻을 수 있다는 장점이 있지만, 공격코드를 구현하기 어렵다는 단점이 있다. 본 논문에서는 공격코드들의 구조를 분석하여 공통된 부분들을 모듈화하고 이를 재사용함으로써 다양한 취약점을 정확하게 점검할 수 있고, 새로운 취약점에 대해서도 쉽게 확장할 수 있는 취약점 증명을 위한 프레임워크를 제시한다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.9
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• pp.14-24
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• 2009

Memory cell array and peripheral circuits are designed for system on panel style frame buffer. Moreover, a parallel test methodology to test multiple blocks of memory cells is proposed to overcome low yield of system on panel processing technologies. It is capable of faster fault detection compared to conventional memory tests and also applicable to the tests of various embedded memories and conventional SRAMs. The various patterns of conventional test vectors can be used to enhance fault coverage. The proposed testing method is also applicable to hierarchical bit line and divided word line, one of design trends of recent memory architectures.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.6B
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• pp.1059-1067
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• 1999

In this paper characteristics of ATM-PON is described and a TC layer controller for ATM-PON OLT is designed. This paper proposes an algorithm of economically controlling the grant information written by CPU to dynamically allocate the upstream bandwidth on the PON among the ONUs in a fair way and of encrypting the downstream data using a lower standard of encryption, termed data churning, which is used to distinguish it from existing transmission system scramblers and higher layer encryption methods. This paper also proposes a method of allocating churning-related message into the PLOAM cell in order to synchronously change the churning key between the OLT and the ONU.

• The Journal of the Korea Contents Association
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• v.7 no.12
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• pp.238-244
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• 2007

Guaranteed Frame Rate(GFR), recently approved by the ATM Forum, expects to become an important service category to efficiently support TCP/IP traffic in ATM networks. The GFR service not only guarantees a minimum service rate at the frame level, but also supports a fair share of available bandwidth. We proposed new scheduling scheme for the GFR service. Proposed scheme provides priority to VCs and high priority to a VC which have more untagged cells in buffer. High priority VCs have much more serviced than low priority. Proposed scheme can provide MCR(minimum cell rate) guarantee and fair sharing to GFR VCs. Computer simulation results show that proposed scheduling scheme provide a much better performance in TCP goodput and fairness than previous scheme.

• Journal of the Korea Society of Computer and Information
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• v.4 no.4
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• pp.155-162
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• 1999

Various applications of video conferencing are required real-time transmission in order to offer service of best effort in internet. Because the bandwidth of internet changes dynamically, appropriated QoS could not be guaranteed To resolve the problem. available bandwidth between sender and receiver is measured. And according to measured bandwidth, the transmission of multimedia data is controlled In this paper, we propose algorithm of efficient transmission for best QoS in internet According to a present status of network, we measure available bandwidth using feedback RTCP information and change a compression rate to reduce a producing CODEC data. And according to the priority that is measured by packet loss for received RTCP information, we abandon frames indicated as lower weight in transmission buffer of sender.

• Proceedings of the Korean Information Science Society Conference
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• 2005.11b
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• pp.907-909
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• 2005

체감형 게임의 재미를 극대화 하기 위해서 몰입감있는 게임화면이 제공되어야 한다. 곡면, 반구형 스크린은 일반 평면 스크린을 사용할 때 보다 더 높은 몰입감을 줄 수 있지만 투사시 생기는 왜곡영상 보정에 많은 계산이 요구되는 문제가 있다. 정지된 영상(프리젠테이션 화면)이나 비디오 영상은 메모리 버퍼링을 통해 시스템이 요구하는 속도를 보장할 수 있으나, 사용자와 상호작용이 요구되는 게임에서는 사용자의 반응을 처리한 후 매 프레임 마다 빠른 워핑(warping) 처리를 요구하게 되는데, 렌더링될 화면을 미리 보정할 수가 없기 때문에 시스템 처리속도 저하의 원인이 된다. 본 논문에서는 체감형 게임을 곡면에 투사하는 방법과 GPU를 이용한 빠른 영상 보정을 제안함으로써 게임에서 요구하는 처리 속도를 보장하고 고해상도의 게임화면을 사용할 수 있도록 했다. 웹카메라를 이용하여 스크린과 프로젝터될 영상간의 호모그래피(homographpy)를 정의해서 워핑했고 워핑 연산을 HLSL로 작성하여 GPU를 이용했다. 실험결과로 반구형 스크린에서 몰입감 있는 AR 탁구게임을 보인다.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.3
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• pp.14-21
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• 1989

In the digital transmission equipment, the input jitter tolerance is a function of input timing recovery circuit characteristics. Especially, in the asynchronous multiplexers, it is also a function of the frame format, the buffer sizes in the synchronizer and desynchronizer, the PLL transfer function, and operating range of VCO in PLL In this paper, a new algorithm for calculating the jitter tolerance of the saynchronous digital transmission equipment is presented. With the new algorithm, we analyzed how the above factors limit the jitter tolerance in the equipment. We also measured the input jitter tolerance for a 45M-140M multiplexing equipment, whose results show the same trend with calculated tolerance.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.2
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• pp.151-156
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• 2017

Communication performance requirements are described as QoS parameters in multimedia communication Protocols including SCTP. One of the important QoS parameters is the reliability of the transfer. As a QoS parameter, the reliability defines error detection, report and correction mechanisms. Including SCTP, conventional error control mechanisms, however, do not consider the integrated viewpoint of multimedia data. In this paper, I have designed and proposed the multimedia oriented error control method based on multimedia characteristics. The proposed scheme should have the reduction effect of the communication resources such as frame buffer, procesing power and bandwidth as well as satisfy the requirements of users.

• Journal of Korea Multimedia Society
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• v.5 no.6
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• pp.697-703
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• 2002

In this paper, we propose the adaptive multi stream transmission technique based on SPIHT video signal for the highest quality service over the current Internet that does not guarantee QoS. In addition to the reliable transmission of the video stream over the asynchronous packet network, the proposed approach provides the transmission using the adaptive frame pattern control and multi steam over the TCP for continuous replay. The adaptive frame pattern control makes the transmission date scalable in accordance with the client's buffer status. Apart from this, the multi stream transmission improves the efficiency of video stream, and is robust to the network jitter problem, and maximally utilizes the bandwidth of the client's. As a result of the experiment, the DR(delay ratio) in the proposed adaptive multi-stream transmission is more close to zero than in the existing signal stream transmission, which enables the best-efforts service to be implemented.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.12
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• pp.201-208
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• 2012

In this paper, the hardware design of rate control for real-time video encoded is proposed. In the proposed method, a quadratic rate distortion model with high-computational complexity is not used when quantization parameter values are being decided. Instead, for low-computational complexity, average complexity weight values of frames are used to calculate QP. For high speed and low computational prediction, the MAD is predicted based on the coded basic unit, using spacial and temporal correlation in sequences. The rate control is designed with the hardware for fast QP decision. In the proposed method, a quadratic rate distortion model with high-computational complexity is not used when quantization parameter values are being decided. Instead, for low-computational complexity, average complexity weight values of frames are used to calculate QP. In addition, the rate control is designed with the hardware for fast QP decision. The execution cycle and gate count of the proposed architecture were reduced about 65% and 85% respectively compared with those of previous architecture. The proposed RC was implemented using Verilog HDL and synthesized with UMC $0.18{\mu}m$ standard cell library. The synthesis result shows that the gate count of the architecture is about 19.1k with 108MHz clock frequency.