• Journal of Korea Soil Environment Society
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• v.1 no.1
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• pp.89-102
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• 1996

An integrated model is presented to describe underground flow and mass transport, using a multicomponent multiphase approach. The comprehensive governing equation is derived considering mass and force balances of chemical species over four phases(water, oil, air, and soil) in a schematic elementary volume. Compact and systemati notations of relevant variables and equations are introduced to facilitate the inclusion of complex migration and transformation processes, and variable spatial dimensions. The resulting nonlinear system is solved by a multidimensional finite element code. The developed code with dynamic array allocation, is sufficiently flexible to work across a wide spectrum of computers, including an IBM ES 9000/900 vector facility, SP2 cluster machine, Unix workstations and PCs, for one-, two and three-dimensional problems. To reduce the computation time and storage requirements, the system equations are decoupled and solved using a banded global matrix solver, with the vector and parallel processing on the IBM 9000. To avoide the numerical oscillations of the nonlinear problems in the case of convective dominant transport, the techniques of upstream weighting, mass lumping, and elementary-wise parameter evaluation are applied. The instability and convergence criteria of the nonlinear problems are studied for the one-dimensional analogue of FEM and FDM. Modeling capacity is presented in the simulation of three dimensional composite multiphase TCE migration. Comprehesive simulation feature of the code is presented in a companion paper of this issue for the specific groundwater or flow and contamination problems.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.12 no.5
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• pp.467-474
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• 2019

In this paper, we propose a novel method to improve FPS while maintaining the accuracy of YOLO v2 model in NVIDIA Jetson TX1. In general, in order to reduce the amount of computation, a conversion to an integer operation or reducing the depth of a network have been used. However, the accuracy of recognition can be deteriorated. So, we use methods to reduce computation and memory consumption through adjustment of the filter size and integrated computation of the network The first method is to replace the $3{\times}3$ filter with a $1{\times}1$ filter, which reduces the number of parameters to one-ninth. The second method is to reduce the amount of computation through CBR (Convolution-Add Bias-Relu) among the inference acceleration functions of TensorRT, and the last method is to reduce memory consumption by integrating repeated layers using TensorRT. For the simulation results, although the accuracy is decreased by 1% compared to the existing YOLO v2 model, the FPS has been improved from the existing 3.9 FPS to 11 FPS.

• Journal of IKEEE
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• v.26 no.4
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• pp.633-638
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• 2022

Rencently, neuromorphic systems of spiking neural networks (SNNs) that imitate the human brain have attracted attention. Neuromorphic technology has the advantage of high speed and low power consumption in cognitive applications and processing. Resistive random-access memory (RRAM) for SNNs are the most efficient structure for parallel calculation and perform the gradual switching operation of spike-timing-dependent plasticity (STDP). RRAM as synaptic device operation has low-power processing and expresses various memory states. However, the integration of RRAM device causes high switching voltage and current, resulting in high power consumption. To reduce the operation voltage of the RRAM, it is important to develop new materials of the switching layer and metal electrode. This study suggested a optimized new structure that is the Metal/Al₂O₃/HfO_x/SWCNTs/N+silicon (MOCS) with single-walled carbon nanotubes (SWCNTs), which have excellent electrical and mechanical properties in order to lower the switching voltage. Therefore, we show an improvement in the gradual switching behavior and low-power I/V curve of SWCNTs-based memristors.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.4
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• pp.144-154
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• 2013

This paper proposes a new super-resolution algorithm where sharpness enhancement is merged in order to improve overall visual quality of up-scaled images. In the learning stage, multiple dictionaries are generated according to sharpness strength, and a proper dictionary among those dictionaries is selected to adapt to each patch in the inference stage. Also, additional post-processing suppresses boosting of artifacts in input low-resolution images during the inference stage. Experimental results that the proposed algorithm provides 0.3 higher CPBD than the bi-cubic and 0.1 higher CPBD than Song's and Fan's algorithms. Also, we can observe that the proposed algorithm shows better quality in textures and edges than the previous works. Finally, the proposed algorithm has a merit in terms of computational complexity because it requires the memory of only 17% in comparison with the previous work.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.1
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• pp.37-44
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• 2009

This paper describes a new tiled display framework called, iTDF (Interactive Tiled Display Framework), that is designed to support rapid construction of the interactive digital 3D contents running on top of the cluster-based tiled display. This framework allows synchronizing the rendering slaves, sharing software's state over the network, the features, such as, launching multiple applications on a cluster-based computers, moving and resizing windows, synchronization of rendering slaves, distributed shared memory, and unified input interface. This paper analyzes the requirements of the framework and describes the design and implementation of the framework. A couple desktop-based applications are ported with the new iTDF and to find out the usefulness and usability of the framework.

• The KIPS Transactions:PartC
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• v.12C no.4 s.100
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• pp.503-510
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• 2005

With the increasing importance of network protection from cyber threats, it is requested to develop a multi-gigabit rate pattern matching method for protecting against malicious attacks in high-speed network. This paper devises a high-speed pattern matching algorithm with TCAM by using an m-byte jumping window pattern matching scheme. The proposed algorithm significantly reduces the number of TCAM lookups per payload by m times with the marginally enlarged TCAM size which can be implemented by cascading multiple TCAMs. Due to the reduced number of TCAM lookups, we can easily achieve multi-gigabit rate for scanning the packet payload. It is shown by simulation that for the Snort nile with 2,247 patterns, our proposed algorithm supports more than 10 Gbps rate with a 9Mbit TCAM.

• Journal of KIISE:Computing Practices and Letters
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• v.10 no.5
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• pp.385-393
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• 2004

Cluster systems have been widely used for solving problems in various application domains, and regarded as useful high performance computing resources. As the number of cluster system user is increasing, it is no less important to maintain stable operation than to improve cluster system performance. Although hardware preventive maintenance is important for keeping normal operation, the testing tool which can be used for general cluster systems during maintenance has received little attention. In this Paper, considering hardware Preventive maintenance, we suggest a testing tool for hardware of cluster system. The cluster system testing tool which is named CTS(Cluster system Test Suite) has two check routines; one for memory, and the other for NIC respectively. The CTS is designed to support the common features of general cluster systems and all the Jobs such as setting test conditions to querying the results can be done entirely within an integrated GUI environment. CTS is used as the testing tool for two kinds of cluster systems during maintenance, and the experimental results show that CTS reports useful information for cluster systems management.

• Journal of Korea Multimedia Society
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• v.12 no.10
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• pp.1499-1507
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• 2009

With the abundance of digital contents, the necessity of precise indexing technology is consistently required. To meet these requirements, the intelligent software entity needs to be the subject of information retrieval and the interoperability among intelligent entities including human must be supported. In this paper, we analyze the unifying framework for multi-modality indexing that Snoek and Worring proposed. Our work investigates the method of improving the authenticity of indexing information in contents-based automated indexing techniques. It supports the creation and control of abstracted high-level indexing information through ontological concepts of Semantic Web skills. Moreover, it attempts to present the fundamental model that allows interoperability between human and machine and between machine and machine. The memory-residence model of processing ontology is inappropriate in order to take-in an enormous amount of indexing information. The use of ontology repository and inference engine is required for consistent retrieval and reasoning of logically expressed knowledge. Our work presents an experiment for storing and retrieving the designed knowledge by using the Minerva ontology repository, which demonstrates satisfied techniques and efficient requirements. At last, the efficient indexing possibility with related research is also considered.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.42 no.2
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• pp.316-322
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• 2017

This paper suggests an efficient software implementation of lightweight encryption algorithm PRESENT which supports for secret key lengths of 80-bits. Each round of PRESENT is composed of the round key addition, substitution, and permutation and is repeated 31 times. Bo Zhu suggested combined substitution and permutation for efficient operation so that encryption throughput has been increased 2.6 times than processing substitution and permutation at separate times. The scheme that suggested in this paper improved the scheme of Bo Zhu to reduce the number of operation for the round key addition, substitution, and permutation. The scheme that suggested in this paper has increased encryption throughput up to 1.6 times than the scheme of Bo Zhu but memory usage has been increased.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.36S no.11
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• pp.34-43
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• 1999

A high-speed image processor (HIP) is implemented for a high-speed multi-function peripheral. HIP has a binarization architecture with unified data path. It has the pixel-by-pixel pipelined processing to minimize size of the external memory. It performs pre-processing such as shading correction, automatic gain control (AGC), and gamma correction, and also drives external CCD or CIS modules. The pre-processed data can be enlarged or reduced. Various binarizatin algorithms can be processed in the unified archiecture. The embedded binarization algorithms are simple thresholding, high pass filtering, dithering, error diffusion, and thershold modulated error diffusion. These binarization algorithms are unified based on th threshold modulated error diffusion. The data path is designed to share the common functional block of the binarization algorithms. The complexity of the controls and the gate counts is greatly reduced with this novel architecture.