• Proceedings of the Korean Information Science Society Conference
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• 2002.04a
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• pp.616-618
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• 2002

최근에는 고성능 네트웍으로 구성된 클러스터 상에서 사용자 수준 통신을 사용하는 소프트웨어 분산 공유메모리 시스템의 연구가 활발히 진행되고 있다. 본 논문에서는 사용자수준 프로토콜의 표준인 Virtual Interface Architecture(VIA)를 사용하고 확장성 있는 Home-based Lazy release Consistency(HLRC) 모델을 기반으로 하는 소프트웨어 분산공유메모리 시스템을 구현한다. 본 시스템은 VIA의 원격 메모리 쓰기 기능을 최대한 활용하며, 통신 과정에서 통신 버퍼와 사용자 메모리 사이의 복사가 일어나지 않도록 설계되어 높은 성능을 보인다.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.38 no.10
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• pp.24-33
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• 2001

Delay, delay variation and packet loss rate are principal QoS(Quality of Service) elements of packet communication. This paper proposes a new buffer allocation mechanism to improve the packet loss performance in such a situation that multiple logical buffers share a single physical memory buffer. In the proposed buffer allocation mechanism, the movement of dynamic threshold follows a curved track instead of a straight line which is used in the DT(dynamic threshold) mechanism. In order evaluate the effectiveness of the proposed mechanism, it is compared with the existing previously proposed mechanisms in several aspects including NC(no control), ST(Static Threshold) and DT mechanisms.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2001.05a
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• pp.269-274
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• 2001

This paper is study of buffering system for multimedia server. We propose the scheme that increasing the performance of multimedia sever by using the buffer sharing scheme and slot addressing algorithm to maximize fixed buffer utilization. Also, we calculate reference time about a used block and next stream reuse that stram. As a result, we propose the buffering system satisfy the users request using the extra bandwidth that reducing multimedia server I/O.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.39B no.2
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• pp.86-94
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• 2014

Optical packet switching (OPS) is being considered as one of the switching technologies for a future optical internet. For contention resolution in an optical packet switching (OPS) system, the wavelength dimension is generally used in combination with a fiber delay line (FDL) buffer. In this article, we propose a method to reduce the number of tunable wavelength converters (TWCs) by sharing TWCs for a cost-effective design of an asynchronous OPS system with a shared or an output FDL buffer. Asynchronous and variable-length packets are considered in the OPS system design. To investigate the number of TWCs needed for the OPS system, an algorithm is proposed, which searches for an available TWC and an unused internal wavelength, as well as an outgoing channel. This algorithm is applied to an OPS system with a shared or an output FDL buffer. Also, the number of internal wavelengths (i.e., the conversion range of the TWC) needed for an asynchronous OPS system is presented for cost reduction of the OPS system.

• Proceedings of the Korea Association of Information Systems Conference
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• 1997.10b
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• pp.215-227
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• 1997

데이터베이스 공유 시스템(database sharing system)은 고성능의 트랜잭션 처리를 위한 시스템으로서, 별도의 메모리와 운영체제 그리고 데이터베이스 관리 시스템(DBMS)을 가진 처리 노드와 고속의 통신 시스템으로 구성된다. 공유 데이터는 다수의 DBMS에 의해 동시에 캐싱 될 수 있으므로 처리노드 간의 일관성 유지를 위해 동시성 제어(concurrency control)와 일관성 제어(coherency control) 기법이 필요하다. 본 연구에서는 동적 PCA 관 리 방식과 이를 위한 버퍼 무효화 기법을 제안한다. 제안된 동적 PCA 관리 방식은 시스템 환경의 변화에 대한 적응성을 제공한다. 또한 공유 데이터의 일관성 유지를 위한 세 가지의 버퍼 무효화 기법은 디스크 I/O 오버헤드와 메시지 전송량을 감소함으로써 동적 PCA 관리 를 효율적으로 지원할 수 있다.

• Journal of the Korea Society for Simulation
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• v.28 no.2
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• pp.119-129
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• 2019

Although line production systems with finite buffers have been studied over several decades, except for some special cases there are no explicit expressions for system performances such as waiting times(or response time) and blocking probability. Recently, a max-plus algebraic approach for buffer-sharing systems with constant processing times was introduced and it can lead to analytic expressions for (higher) moment and tail probability of stationary waiting. Theoretically this approach can be applied to general processing times, but it cannot give a proper way for computing performance measures. To this end, in this study we developed simulation models using @RISK software and the expressions derived from max-plus algebra, and computed and compared blocking probability, waiting time (or response time) with respect to two blocking policies: communication(BBS: Blocking Before Service) and production(BAS: Blocking After Service). Moreover, an optimization problem which determines the minimum shared-buffer capacity satisfying a predetermined QoS(quality of service) is also considered.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.7C
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• pp.664-669
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• 2002

In this paper, we propose the fuzzy control algorithm for effective buffer control to connected traffic in ATM networks. The proposed Fuzzy control algorithm has two priorities and uses Fuzzy sets to search for dynamic thresholds. In this words, the difuzzification value controls the threshold in the buffer to according to traffic priority (low or high) using fuzzy set theory for traffic connected after reasoning. Performance analysis result: it was confirmed that with the proposed scheme, performance improves at cell loss rate, when compared with the existing PBS scheme.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.56 no.4
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• pp.784-789
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• 2007

This paper presents an implementation of a new type of architecture to improve an overflow problem on the network buffer. Each receiver channel of network system stores the message in its own buffer. If some receiver channel receives many messages, buffer overflow problem may occur for the channel. This paper proposes a network controller that implements a receiver channel with shared-memory to save all of the received messages from the every incomming channels. The proposed architecture is applied to ARINC-429, a real-time control network for commercial avionics system. For verifying performance of the architecture, ARINC-429 controller is designed using a SOPC platform, designed by Verilog and targeted to Xilinx Virtex-4 with a built-in PPC405 core.

• Journal of KIISE:Computer Systems and Theory
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• v.33 no.11
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• pp.810-819
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• 2006

This paper proposes an Adaptive Double Buffer Model. As a new FIFO buffer model, this technique minimizes packet losses from network congestion by logically managing buffers. It allocates the spare spaces of non-congested buffers to congested buffers by allowing receive/send buffers to share two queues, and hence it minimizes packet losses. In contrast to the buffer model utilizing a free list, this buffer model can prevent the bubble phenomenon caused by a memory leak and thereby apply to a network buffer in a restricted environment. Also, compared with the model using an way, this model brings maximum 100 percent improvement in accepting packets and compared with the model utilizing a free list, this model has the similar efficiency Results of the performance test on Adaptive Double Buffer Model, shows that this proposed model decreases packet losses and enhances memory efficiency.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.7
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• pp.1497-1501
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• 2005

Branch instructions which make the sequential instruction flow changed cause pipeline stalls in microprocessor. The pipeline hazard due to branch instructions are the most serious problem that degrades the performance of microprocessors. Branch target buffer predicts whether a branch will be taken or not and supplies the address of the next instruction on the basis of that prediction. If the hanch target buffer predicts correctly, the instruction flow will not be stalled. This leads to the better performance of microprocessor. In this paper, the architecture of a ta8 memory that branch target buffer and TLB can share is presented. Because the two tag memories used for branch target buffer and TLB each is replaced by single combined tag memory, we can expect the smaller chip size and the faster prediction. This shared tag architecture is more advantageous for the microprocessors that uses more bits of address and exploits much more instruction level parallelism.