• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.43 no.1 s.343
• /
• pp.71-78
• /
• 2006

An NoC (Networks-on-Chip) is an emerging design paradigm intended to cope with a future SoC containing numerous built-in cores. In an NoC, the test strategy is very significant for its practicality and feasibility. Among existing test issues, TAM architecture and test scheduling will particularly dominate the overall test performance. In this paper, we address an efficient NoC test scheduling algorithm based on a rectangle packing approach used for an SoC test. In order to adopt the rectangle packing solution as an NoC test scheduling algorithm we design the configuration about test resources and test methods suitable for an NoC structure. Experimental results using some ITC'02 benchmark circuits show the proposed algorithm can reduce the overall test time by up to $55\%$ in comparison with previous works.

• Journal of KIISE:Computer Systems and Theory
• /
• v.29 no.6
• /
• pp.361-368
• /
• 2002

This paper presents a new data path synthesis algorithm which takes into account simultaneously three important design criteria: testability, design area, and total execution time. We define a goodness measure on the testability of a circuit based on three rules of thumb introduced in prior work on synthesis for testability. We then develop a stepwise refinement synthesis algorithm which carries out the scheduling and allocation tacks in an integrated fashion. Experimental results for benchmark and other circuit examples show that we are able to enhance the testability of circuits with very little overheads on design area and execution time.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.45 no.2
• /
• pp.93-100
• /
• 2008

In this paper, we address a novel simulated annealing(SA)-based test scheduling method for testing network-on-chip (NoC)-based systems-on-chip(SoCs), on the assumption that the test platform proposed in [1] is installed. The proposed method efficiently mixed the rectangle packing method with SA and improved the scheduling results by locally changing the test access mechanism(TAM) widths for cores and the testing orders. Experimental results using ITC'02 benchmark circuits show that the proposed algorithm can efficiently reduce the overall test time.

• Journal of Digital Contents Society
• /
• v.9 no.3
• /
• pp.471-481
• /
• 2008

Test scheduling considering power dissipation is an effective technique to reduce the testing time of complex SoCs and to enhance fault coverage under limitation of allowed maximum power dissipation. In this paper, a modeling technique of test resources and a test scheduling algorithm for efficient test procedures are proposed and confirmed. For test resources modeling, two methods are described. One is to use the maximum point and next maximum point of power dissipation in test resources, the other one is to model test resources by partitioning of them. A novel heuristic test scheduling algorithm, using the extended-tree-growing-graph for generation of maximum embedded cores usable simultaneously by using relations between test resources and cores and power-dissipation-changing-graph for power optimization, is presented and compared with conventional algorithms to verify its efficiency.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.48 no.8
• /
• pp.42-50
• /
• 2011

Recently, research activities on the future internet are being actively performed in foreign and domestic. In domestic, ETRI and 4 universities are focused on implementation of a testbed for research on the future internet named as 'FiRST(Future Internet Research for Sustainable Testbed)'. In the 'FiRST' project, 4 universities are performing a project in collaboration named as 'FiRST@PC' project that is for an implementation of the testbed using the programmable platform-based openflow switches. Currently, the research on the virtualization of the testbed is being performed that has a purpose for supporting an isolated network to individual researcher. In this paper, we implemented a traffic scheduler for providing QoS by using the programmable platform that performs a hardware-based packet processing and we are implemented a testbed using that traffic scheduler. We perform a performance evaluation of the traffic scheduler on the testbed. As a result, we show that the hardware-based NetFPGA scheduler can provide reliable and stable QoS to virtualized networks of the Future Internet Testbed.

• Proceedings of the Korean Society of Broadcast Engineers Conference
• /
• 2009.11a
• /
• pp.403-405
• /
• 2009

통방융합 환경에서 Killer 서비스로 각광을 받고 있는 VOD(Video On Demand)서비스에서 I/O 병목현상은 VOD 서버의 오 동작 및 성능 저하의 주요 원인이 되고 있다. 본 논문에서는 이런 I/O 병목 현상을 개선하여 입출력 효율이 좋은 고성능 VOD 솔루션을 제안한다. 제안된 솔루션은 대용량 더블 버퍼를 구성하여 하나의 버퍼로 클라이언트에 데이터를 전송하고 있는 사이에, 나머지 다른 버퍼에서 스토리지에서 전송되는 데이터를 버퍼에 저장 하여, 디스크 접근 시 한번에 보다 많은 데이터를 읽음으로써 연속적인 정보를 가져올때 빈번하게 하드디스크의 접근을 줄임으로서 끊김없는 전송을 가능하게 한다. 또한 다수의 사용자가 동시 접근 시 데이터 충돌을 방지하고, 스토리지에 순차적으로 연속 접근하도록 접근 발생 시간에 따라 우선 순위 인덱스를 할당하고 회수하도록 스토리지 접근 스케쥴러를 고안 하였다. 제안된 솔루션의 유효성을 검증하기 위해 SD급 콘텐츠에 대해 솔루션의 Throughoutput 처리량을 벤치마킹 테스트로 검증을 하였다. 테스트 결과 MPEG-2 SD급 영상에대해 Raid 5에서 최대 1000 스트리밍을 전송 할 수 있음을 확인 하였다.

• Journal of the Korea Society for Simulation
• /
• v.19 no.1
• /
• pp.1-11
• /
• 2010

K company produces semiconductor package products under the make-to-order policy to supply for domestic and foreign semiconductor manufacturing companies. Its production process is a machine-paced assembly line type, which consists of die sawing, assembly, and test. This paper suggests three plans to increase process throughput based on the process analysis of K company and evaluates them via a simulation model using a real data collected. The three plans are line balancing by adding machines to the bottleneck process, product group scheduling, and reallocation of the operators in non-bottleneck processes. The evaluation result shows the highest daily throughput increase of 17.3% with an effect of 2.8% reduction of due date violation when the three plans are applied together. Payback period for the mixed application of the three plans is obtained as 1.37 years.

• Journal of KIISE:Computer Systems and Theory
• /
• v.37 no.6
• /
• pp.339-347
• /
• 2010

Inter-process communication (IPC), which is a technique that enables exchanging data among multiple processes, is commonly used not only in user applications but also in system processes. For this reason, the performance of IPC highly influences the performance of whole computer system. Especially, heavy overload on a single server process caused by IPC requests from multiple client processes, easily results overall slowdown of IPC response time. Here, to deal with the problem stated above, the time-slice donation technique which is adapted in L4 microkernel is analyzed and enhanced for reducing latency of IPC response time and implemented on linux kernel for actual performance evaluation. While trying to maintain the additional overhead as least as possible, the experiment shows that the use of this technique enhances the performance of IPC multiple times of existing technique under certain circumstances.

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.36C no.7
• /
• pp.36-45
• /
• 1999

In order to control the flow of traffics in ATM networks and optimize the usage of network resources, an efficient control mechanism is necessary to cope with congestion and prevent the degradation of network performance caused by congestion. In this paper, Buffered Leaky Bucket which applies the same control scheme to a variety of traffics requiring the different QoS(Quality of Service) and Neural Networks lead to the effective buffer utilization and QoS enhancement in aspects of cell loss rate and mean transfer delay. And the cell scheduling algorithms such as DWRR and DWEDF for multiplexing the incoming traffics are enhanced to get the better fair delay. The network congestion information from cell scheduler is used to control the predicted traffic loss rate of Neural Leaky Bucket, and token generation rate and buffer threshold are changed by the predicted values. The prediction of traffic loss rate by neural networks can enhance efficiency in controlling the cell loss rate and cell transfer delay of next incoming cells and also be applied for other traffic controlling schemes. Computer simulation results performed for random cell generation and traffic prediction show that QoSs of the various kinds of traffcis are increased.