• Transactions on Semiconductor Engineering
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• v.2 no.3
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• pp.1-5
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• 2024

This paper presents a crystal-less reference clock recovery (CR) frequency synthesizer with compensation designed for Bluetooth Low Energy (BLE) Smart-tag applications, operating at frequencies of 32, 72, and 80MHz. In contrast to conventional frequency synthesizers, the proposed design eliminates the need for external components. Using a single-ended antenna to receive a minimal input power of -36dBm at a 2.4GHz signal, the CR synthesizes frequencies by processing the RF signal received through a Low Noise Amplifier ( L N A ) . This approach allows the system to generate a reference clock without relying on a crystal. The received signal is amplified by the LNA and then input to a 16-bit ACC (Automatic Clock Compensation) circuit. The ACC compares the frequency of the received signal with the oscillator output signal, using the synthesis of a 32MHz reference clock through a frequency compensation method. The oscillator is constructed using a Ring Oscillator (RO) with a Frequency Divider, offering three different frequencies (32/72/80MHz) for various system components. The proposed frequency synthesizer is implemented using a 55-nm CMOS process.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.10
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• pp.1537-1544
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• 2022

When designing chip, it considers design specification, timing problem, and clock synchronization on place & route (P&R) process. P&R process is complicated because of considering various factors. Chip uses clock tree synthesis (CTS) to reduce clock path delay. The purpose of this study is to examine shallow-CTS algorithm for checking clock tree synthesizable. Using open source Parser-Verilog, register transfer level (RTL) synthesizable Verilog file is parsed and it uses Pre-CTS and Post-CTS process that is included shallow-CTS. Based on longest clock path in the Pre-CTS and Post-CTS stages, the standard deviation before and after buffer insertion is compared and analyzed for the accuracy of CTS. In this paper, It is expected that the cost and time problem could be reduced by providing a pre-clock tree synthesis verification method at the RTL level without confirming the CTS result using the time-consuming licensed EDA tool.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.14 no.4
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• pp.338-347
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• 1989

In this paper, the digital frequency synthesizer with the clock ccunting method is designed and implemented to increase the performace of the digital frequency synthesizer with pahse accumulating method which was developed before. Unlike an phase accumulating method, clock countind method is supplied a continually changeable clock frequency with PLL(Phase Locked Loop) and allocated a fixed phase step with N-ary counter. Form the experimenta results, it is confirmed that any periodic distorition phenomena are disappeared, and truncation harmonics are more reduced. But the output bandwidths are decreased in inverse proportion to the counter counting number and the circuits are somewhat complex than phase accumulating method.

• Journal of IKEEE
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• v.26 no.4
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• pp.714-721
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• 2022

A phase-locked loop (PLL)-based frequency synthesizer is proposed for a system on a chip (SoC) using multi-frequency clock signals. The proposed PLL-based frequency synthesizer consists of a charge pump PLL which is implemented by a phase frequency detector (PFD), a charge pump (CP), a loop filter, a voltage controlled oscillator (VCO), and a frequency divider, and an edge combiner. The PLL outputs a 12-phase clock by a VCO using six differential delay cells. The edge combiner synthesizes the frequency of the output clock through edge combining and frequency division of the 12-phase output clock of the PLL. The proposed PLL-based frequency synthesizer is designed using a 55-nm CMOS process with a 1.2-V supply voltage. It outputs three clocks with frequencies of 166 MHz, 83 MHz and 124.5MHz for a reference clock with a frequency of 20.75 MHz.

• Proceedings of the Korea Information Processing Society Conference
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• 2005.05a
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• pp.481-484
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• 2005

본 논문에서는 부동소수점 연산을 사용하면서도 빠른 처리속도를 가지는 신경망의 파이프라인 설계를 제안한다. 부동소수점 연산은 고정소수점 연산보다 느린 처리속도와 많은 면적으로 일반적인 하드웨어 구현에서 잘 사용되지 않지만, 제안된 구조에서는 고정소수점 연산보다 더 정확한 값을 계산할 수 있는 부동소수점 연산을 사용하며 부동소수점의 느린 처리 속도를 보완할 수 있도록 파이프라인 구조를 사용한다. 파이프라인 구조의 성능을 검증하기 위해 2 가지의 서로 다른 구조의 신경망을 사용한다. 실험 환경으로는 Xilinx XC2V8000 칩과 Xilinx ISE 6.2 의 합성 도구를 사용한다. 실험 결과는 파이프라인 구조일 때의 신경망은 각각 7 클럭, 8 클럭이 소요되고, 파이프라인 구조가 아닐 때 각각의 신경망은 77 클럭, 84 클럭으로써 파이프라인 구조일 때 약 10 배의 빠른 처리를 가진다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.8
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• pp.2064-2071
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• 1998

A new digital clock level translator has been designed in order to produce a clock source of the internal logic circuits. The translator output has 50% duty ratio from small sinusoidal input such as TCXO which oscillates itself in poratable components. The circuit consists of positive and negative comparators, RS latch, charge pump, and reference vol- tage generator. It detects pulse width of the output waveform and feedbacks the control signal to the input com-parator. It detects pulse width of the output waveform and feedbacks the control signal to the input com-parator reference, producing output waveform with valid 50% duty ratio of the digital signal level. The designed level translator can be used as a sampling clock source of ADC, PLL and the colck source of the clock synthesizer. The circuit wasdesigned in a 0.8.mu.m analog CMOS technology with double metal, double poly, and BSIM3 circuit simulation model. From our experimental results, a stable operating characteristics of 50 +3% duty ratio was obtained from the sinusoidal input wave of 370 mV.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.2
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• pp.104-110
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• 2003

A new direct digital frequency synthesizer (DDFS) is proposed. The DDFS uses a new ROM compression method that divides each ROM in the conventional DDFS into two ROMs (a quantization ROM and an error ROM). The total size of the ROMs in the proposed DDFS is significantly reduced compared to the original ROM. The ROM compression ratio of 78 is achieved for a DDFS with 12bit output data. A DDFS with 12bit output data for sine function was implemented in a 0.35${\mu}{\textrm}{m}$ CMOS technology. The power dissipation is 9.56㎽ at 100MHz with 3.3V and the maximum operating clock frequency is 330MHz.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.1
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• pp.1038-1041
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• 2005

In today's SoC design, most of IPs which use the different clock frequency from that of the bus require asynchronous FIFOs. However, in many cases, asynchronous FIFO is designed improperly and the cost of the wrong design is high. In this paper, a register-based asynchronous FIFO is designed to transfer data in asynchronous clock domains by using a valid bits scheme that eliminates the problem of the metastability and synchronization altogether. This FIFO architecture is described in HDL and synthesized to the gate level to compare with other FIFO scheme.

• IT SoC Magazine
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• s.3
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• pp.35-37
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• 2004

본 연구팀이 Hynix 0.35um CMOS 4M 2P 공정을 사용하여 제작한 민수용 DDFS (DAC를 포함한 single chip)는 DC부터 100MHz 까지 사용할 수 있으며(BW=100MHz) frequency 변환속도 약 30nS, 주파수해상도 0.0745Hz, 그리고 소비 전력은 120MHz 클럭에서 약 200mW이다. 본고에서는 언급하지 않았지만, 본 연구팀이 별도의 설계로 진행된 군수용 DDFS의 경우, 출력주파수는 DC부터 320MHz 까지 가능하고 소비 전력은 800MHz 클럭에서 약 400mW이다. 이처럼 DDFS는 특성 자체의 우수성 뿐 아니라, 각종 멀티미디어 기기 및 통신시스템의 급격한 디지털화 추세로 인해 주파수합성기도 디지털화 함으로써 VLSI화가 용이하고, 이에 따라 S/W에 의한 다기능화 (programmability), 응용성의 극대화, 및 저가격화를 추구할 수 있다는 점에서 주목해야 할 분야이다. 특히 반도체기술의 발전으로 지금까지 DDFS 구현의 가장 큰 장애로 대두되던 DAC의 고속화가 부분적으로 가능해지면서 (TTL-to-ECL interface 부가회로가 별도로 필요없이 직접적인 연결), DDFS의 시장 전망을 더욱 밝게 하고 있다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.10a
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• pp.289-292
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• 2008

This paper presents a branch prediction algorithm and a 4-way set-associative cache for performance improvement of OpenRISC processor and a clock gating algorithm using ODC (Observability Don't Care) operation for a low-power processor. The branch prediction algorithm has a structure using BTB(Branch Target Buffer) and 4-way set associative cache has lower miss rate than direct-mapped cache. The clock gating algorithm reduces dynamic power consumption. As a result of estimation of performance and dynamic power, the performance of the OpenRISC processor using the proposed algorithm is improved about 8.9% and dynamic power of the processor using samsung $0.18{\mu}m$ technology library is reduced by 13.9%.