• The KIPS Transactions:PartC
• /
• v.16C no.5
• /
• pp.637-644
• /
• 2009

A study about performance analysis of synchronization clock using measured clock noises is required. Therefore this paper executed the study for performance analysis of synchronization clock and acquirement of maximum number of network node with various clock states using measured clock noises in NG-SDH networks. Also this paper generated a suitable clock model using measured clock noises, and carried out simulations with various clock states. Through the simulation results, maximum numbers were 80 or more network nodes in normal state, and were below 37 nodes in short-term phase transient(SPT) state, and were 50 or more in long-term phase transient(LPT) state. Accordingly this study showed that maximum numbers to meet ITU-T specification were below 37 network nodes in three clock states. Also this study showed that when SPT or LPT states occur from NE network before DOTS system, synchronization source must change with other stable synchronization source of normal state.

• Proceedings of the Korean Institute of Communication Sciences Conference
• /
• 1998.10a
• /
• pp.1039-1042
• /
• 1998

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.8 no.6
• /
• pp.1102-1106
• /
• 2004

Main component of phase time error of clocks in communication systems is flicker noise. This paper describes computer simulation algorithm of clock error. First, the standard for clock stability is introduced. Flicker noise is generated from white noise sequences by means of an algorithm. Relation between stage number, time constant and bandwidth are introduced. With the help of this algorithm, flicker noise is generated.

• Proceedings of the Korean Information Science Society Conference
• /
• 1999.10c
• /
• pp.590-592
• /
• 1999

초고속 데이터 처리 및 전송에 필수적인 B-ISDN에 있어서 디지털 시스템들이 동기를 맞추어 동작을 하여야 데이터의 손실과 잡음을 막을 수 있다. 초고속 데이터를 전송하는 ATM 교환기에 있어 동작에 필요한 기준 클럭을 생성하여 시스템 전체에 공급하는 시스템 클럭 생성기는 기능의 안정성과 고신뢰성을 보장하여야 한다. 시스템 클럭 생성기의 운용 중 발생할 수 있는 장애에 대하여 필요한 장애 처리를 수행하기 위하여 내장형 제어용 소프트웨어를 설계하여 구현하였다. 이 제어용 소프트웨어는 시스템 클럭 생성기의 장애를 감시하여 처리하므로 시스템 전체에 클럭의 중단없이 안정되게 ATM교환기를 동작하게 한다. 본 고에서는 ATM 교환기의 시스템 클럭 생성기에서 발생하는 장애 처리를 위한 소프트웨어의 설계와 구현에 관하여 기술한다.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.19 no.11
• /
• pp.2160-2169
• /
• 1994

Main components of phase time error of synchronous network are flicker noise and random walk noise. This paper describe computer simulation of clock error characterized by a statistical model recommended as a standard measure. Flicker noise sequences are generated from white noise sequences by means of a algorithm developed by Barnes. Random-walk noise sequence are obtained by integration of a white noise sequence. Especially for flicker noise, relation between stage number N, time constant ratio K and bandwidth of flicker noise generated was defined by using some examples.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.32 no.6B
• /
• pp.305-315
• /
• 2007

In this paper, We generated a wander generation model from really measured clock noise data on the transmission node and DOTS in NG-SDH network. and then, We presented the performance of Synch. clock and maximum node level capable network configuration through the clock characteristics simulation on network having the steady-state clock.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.26 no.6B
• /
• pp.848-855
• /
• 2001

본 논문에서는 GHz 대역의 고속 클럭 신호를 필요로 하는 데이터 통신 시스템 분야에 응용될 수 있는 새로운 구조의 클럭 및 데이터 복원회로를 제안하였다. 제안된 회로는 고속의 데이터 전송시 주로 사용되는 NRZ 형태의 데이터 복원에 적합한 구조로서 NRZ 데이터가 주입될 경우에 위상동기 회로에 발생하는 주요 잡음원인인 high frequency jitter를 방지하기 위한 새로운 위상 검출구조를 갖추고 있어서 보다 안정적인 클럭을 제공할 수 있다. 또 가변적인 지연시간을 갖는 delay cell을 이용한 위상검출기를 제안하여 위상 검출기가 갖는 dead zone 문제를 없애고, 항상 최적의 동작을 수행하여 빠른 동기 시간을 갖도록 하였다. Gbps급 대용량의 데이터를 복원하기 위한 클럭 생성을 목표로 하여 CMOS 0.25$\mu\textrm{m}$ 공정을 사용하여 설계한 후 그 동작을 HSPICE post-layout simulation을 통해 검증하였다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2004.05b
• /
• pp.583-586
• /
• 2004

In this paper, we have analyzed the performance of synchronization of CCK(Complementary Code Keying) modulation scheme used for IEEE 802.11g wireless LAM system supporting 54 Mbps of high speed data rate over 2.4 GHz. At receiver, the clock frequency offset is caused by noise or fading. This frequency error occurs the offset of clock timing and causes ISI. Therefore the tracking is required to reduce the clock timing offset. The DLL(Delay Lock Loop), asychronization mode, performing tacking the clock is used for the simulation. The simulation result shows jitter variance and BER performance in the AWGN and multipath fading channel environment.

• Transactions on Semiconductor Engineering
• /
• v.2 no.3
• /
• pp.1-5
• /
• 2024

This paper presents a crystal-less reference clock recovery (CR) frequency synthesizer with compensation designed for Bluetooth Low Energy (BLE) Smart-tag applications, operating at frequencies of 32, 72, and 80MHz. In contrast to conventional frequency synthesizers, the proposed design eliminates the need for external components. Using a single-ended antenna to receive a minimal input power of -36dBm at a 2.4GHz signal, the CR synthesizes frequencies by processing the RF signal received through a Low Noise Amplifier ( L N A ) . This approach allows the system to generate a reference clock without relying on a crystal. The received signal is amplified by the LNA and then input to a 16-bit ACC (Automatic Clock Compensation) circuit. The ACC compares the frequency of the received signal with the oscillator output signal, using the synthesis of a 32MHz reference clock through a frequency compensation method. The oscillator is constructed using a Ring Oscillator (RO) with a Frequency Divider, offering three different frequencies (32/72/80MHz) for various system components. The proposed frequency synthesizer is implemented using a 55-nm CMOS process.

• The KIPS Transactions:PartC
• /
• v.13C no.3 s.106
• /
• pp.303-310
• /
• 2006

This paper is to execute a study for characteristic analysis of synchronization clock and maximum network node number with various clock states, normal, SPT, LPT, in NG-SDH networks. Through the simulations, maximum network node numbers showed from 42 to 38 nodes in normal state. In SPT state, maximum network node numbers, when the last NE network applied to only SPT state, presented from 19 to 4 nodes, much less than normal state. Node numbers to meet specification in case of occurrence of SPT state in all NE networks decreased greatly. In LPT state, all maximum node numbers, when the last NE network applied to only LPT state, presented more than 50 nodes, and the results in case of occurrence of LPT state in all NE networks were also identified. However, node numbers to meet specification in case of LPT state in all DOTS networks were few large with difference between LPT and normal or SPT state.