• The Journal of the Korea institute of electronic communication sciences
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• v.10 no.8
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• pp.883-890
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• 2015

As the semiconductor processing technology has been developing, multiple cores or NoC(network on chip) can be contained in recent chips. GALS(globally asychronous locally synchronous) clocking scheme that has multi-clock domains with different frequencies or phase differences is widely used to solve power consumption and clock skew in a large chip with a single clock. A synchronizer is needed to avoid a synchronization problem between sender and receiver in GALS. In this paper, the setup and hold time of DFF required to design the synchronizer are measured using 180nm CMOS processing parameters depending on temperature, supply voltage, and the size of inverter in DFF. The simulation results based on the bisection method in HSPICE show that the setup and hold time are proportional to temperature, however they are inversely proportional to supply voltage, and negative values are measured for the hold time.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.4
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• pp.42-50
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• 2003

This paper presents an embedded RC oscillator which has temperature compensation circuits. The conventional RC oscillator has frequency deviation about 15%, which is caused by variation of resistors and the reference voltage of schmitt trigger from the temperature condition. In this paper, the proposed circuit use a CMOS bandgap reference having balanced current temperature coefficients as a triggering voltage of schmitt trigger. The constant current sources consist of current mirror circuit with the positive and negative temperature coefficient. The proposed circuit shows less 3% frequency deviation for variation of temperature, supply voltage and process parameters.

• Proceedings of the KIEE Conference
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• 2015.07a
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• pp.1251-1252
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• 2015

본 논문에서는 자기 공명 방식 무선전력전송시스템의 전자파 노이즈 원을 분석하기 위해서 근역장 측정 시스템을 이용하여 PCB 회로에 분포하는 근역장 분포를 측정하였다. 측정된 시료는 6.78 MHz를 사용하는 시스템으로 자기 공명 방식으로 에너지를 전송하고 있다. 주 전자파 노이즈 원으로 6.78 MHz의 공진 주파수의 고조파와 시스템에 안정적인 전압을 공급하기 위해 사용되는 레귤레이터의 내부 클럭 신호의 고조파가 많이 발생하고 있다. 이들 고조파 성분은 전 대역의 주파수 영역에 넓게 분포하는 것으로 나타났다.

• Proceedings of the Korean Information Science Society Conference
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• 1998.10c
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• pp.659-661
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• 1998

기존의 평판 디스플레이 비디오 신호 전송 방식은 그래픽 어댑터에 저장된 비디오 데이터를 DA컨버터를 통해 아날로그 신호를 전송한 다음 평판 디스플레이 패널에서 다시 AD 컨버터를 이용해 디지털 신호로 복원한 다음 평판 디스플레이용 컨트롤에 입력되었다. 아날로그 신호를 보내는 것은 AD/DA 컨버터를 이중으로 사용할 뿐 아니라, 연결선을 길게 하는 것이 어렵고 노이즈로 인해 데이터의 수치가 변할 우려가 있다. 패널의 고면적화와 고해상도의 기술 발달로 SXGA급 및 UXGA급 신호에서는 높은 클럭 주파수와 긴 연결선에서도 안정된 신호 전송을 할 수 있는 VESA FPDi 규격에 맞는 인터페이스는 노이즈에 강하고 전자파 발생 억제 및 저전력으로 동작을 한다. 본 논문에서는 인터페이스 신호 전송 방법을 연구하여 신호의 변화를 줄여서 전자파 발생 억제 및 저전력에 도움을 주는 비디오 신호 엔코딩 알고리즘을 제안하였다.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.9 no.1
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• pp.98-107
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• 1998

For implementation of FM-DS/SS system. This paper has analyzed SO(Synchronous Oscillator) being oscillated by the motivation of injected signal. Transmitter has adopted FM-DS/SS modulation method using RF output-signal of FM. Receiver is used SO to demodulation of FM-DS/SS and applied sliding correlator for synchronization of PN clock. As a result of the inspection, SO presented stable lock ability in spite of doppler apperance and proved the synchronous properties of it in the FM-DS/SS system.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.8 s.338
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• pp.43-52
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• 2005

An prescaler which uses PLL(Phase Locked Loop) must satisfy high speed operation and low power consumption. Thus the performance or TSPC(True Single Phase Clocked) D-flip flops which is applied at Prescaler is very important. Power consumption of conventional TSPC D-flip flops was increased with glitches from output and unnecessary discharge at internal node in precharge phase. We proposed a new D-flip flop which reduced two clock transistors for precharge and discharge Phase. With inserting a new PMOS transistor to the input stage, we could prevent from unnecessary discharge in precharge phase. Moreover, to remove the glitch problems at output, we inserted an PMOS transistor in output stage. The proposed flip flop showed stable operations as well as low power consumption. The maximum frequency of prescaler by applying the proposed D-flip flop was 2.92GHz and achieved power consumption of 10.61mw at 3.3V. In comparison with prescaler applying the conventional TSPC D-flip $flop^[6]$, we obtained the performance improvement of $45.4\%$ in the view of PDP(Power-Belay-Product).

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.11C
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• pp.1077-1087
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• 2003

In this paper, we proposed an architecture of a cryptosystem with various operating modes for the network security and implemented in hardware using the ASIC library. For configuring a cryptosystem, the standard block ciphers such as AES, SEED and 3DES were included. And the implemented cryptosystem can encrypt and decrypt the data in real time through the wired/wireless network with the minimum latency time (minimum 64 clocks, maximum 256 clocks). It can support CTR mode which is widely used recently as well as the conventional block cipher modes such as ECB, CBC and OFB, and operates in the multi-bit mode (64, 128, 192, and 256 bits). The implemented hardware has the expansion possibility for the other algorithms according to the network security protocol such as IPsec and the included ciphering blocks can be operated simultaneously. The self-ciphering mode and various ciphering mode can be supported by the hardware sharing and the programmable data-path. The global operation is programmed by the serial communication port and the operation is decided by the control signals decoded from the instruction by the host. The designed hardware using VHDL was synthesized with Hynix 0.25$\mu\textrm{m}$ CMOS technology and it used the about 100,000 gates. Also we could assure the stable operation in the timing simulation over 100㎒ using NC-verilog.

• Convergence Security Journal
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• v.5 no.3
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• pp.23-32
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• 2005

This paper presents a 128-bit Reversible Cellular Automata (RCA) based lightweight block cipher for Ubiquitous computing security. To satisfy resource-constraints for Ubiquitous computing, it is designed as block architecture based on Cellular Automata with high pseudo-randomness. Our implementation requires 704 clock cycles and consumes 2,874 gates for encryption of a 128-bit data block. In conclusion, the processing time outperformed that of AES and NTRU by 31%, and the number of gate was saved by 20%. We evaluate robustness of our implementation against both Differential Cryptanalysis and Strict Avalanche Criterion.

• The Transactions of the Korean Institute of Power Electronics
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• v.10 no.3
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• pp.290-295
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• 2005

The incremental encoder has been mostly used to measure the speed and position of the motor. As the output signals of encoder are high frequency digital signals, they have much influence on radiation noises due to switching of the power semiconductor circuits. It is so difficult to suppress the noises with the conventional LPF. In this paper, the hardware digital filter for suppressing noises in the output signals of the encoder signals is developed. As both the clock frequency and counter in the digital filter for encoder are easily adjusted according to the kinds of noises, any noises in the encoder can be entirely eliminated. The performance of the digital filter has been verified by simulation and experimental results.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.5
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• pp.36-43
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• 1999

A new design of a Direct Digital Frequency Synthesizer(DDFS) is presented, where a pipelined Coordinate Rotate Digital Computer(CORDIC) circuit is employed to calculate amplitude values of all the phase angles of sinusoidal waveforms produced. a near-optimal number of pipeline stages is determined based on an error analysis of calculated amplitude values in terms of the number of bits. The DDFS was implemented using a field programmable gate array, yielding a stable operating frequency of 11.75MHz. The measurement results show higher resolution, faster operating speed and simpler fabrication process, compared to ROM-based counterparts. The CORDIC-based DDFS yields 5 times higher resolution than conventional ROM-based versions.