• Geophysics and Geophysical Exploration
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• v.14 no.4
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• pp.305-315
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• 2011

A total of 864 measurements for P- and S- wave velocity of acrylic and stainless steel core samples have been performed with respect to their lengths and axial load applied. S-wave velocity measurement was much harder than P-wave velocity, so that it showed higher deviation in measured S-wave velocity with respect to repeated measurement, length of the cores, and the axial load applied. Velocity measurements for acrylic cores showed more stable and less than half of the variation between the measurements than the stainless steel cores. This seems to be come from better coupling between the transducers and acrylic cores than stainless cores, and from larger value of the first arrival time in a similar system noise environments. From the analysis of the 864 measurements, it is recommended that the length of the core be 60 ~ 90 mm, axial load between 20 kg (27.7 $N/cm^2$) and 30 kg (41.6 $N/cm^2$) for measurement of wave velocity of the acrylic and stainless steel cores. Especially for measuring S-wave velocity of stainless steel core, core length should be less than 50 mm, otherwise it will be affected by mode conversion or others. These results can be used in measurement and correction for system delay in wave velocity measurement for rock cores.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.12 no.4
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• pp.335-346
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• 1987

The principal reason for the backscattering in an optical fiber is the Rayleigh scattering which is caused by non-uniform density of structure material of an optical fiber and diameter variations of the optical fiber-core along an optical fiber axis. The backscattering signal which is detected by the optical time domain reflectometer system(O.T.D.R) conatains information about both tha actual decay of power and the diameter variation along the optical fiber. In this paper, the O.T.D.R. system with 2x2 fiber directional coupler, timing control unit and gated integrator is used to measure diameter variations of an optical fiber.

• 한국신재생에너지학회:학술대회논문집
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• 2008.10a
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• pp.200-202
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• 2008

동해 울릉분지에서는 시추선 RemEtive를 사용하여 UBGH-X-01 가스하이드레이트 탐사가 2007년에 실시되었다. 본 연구에서는 천부 가스하이드레이트가 확인된 UBGH1-10 정점에서 무인잠수정(Quantam WROV)을 사용하여 획득된 푸쉬코어와 해저지형 분석을 수행되었다.UBGH1-10 정점은 seismic chimneys의 탄성파 특성이 발달된 지역이다. 이곳에서는 해저표면으로부터 수 m 하부에서 가스하이드레이트가 발견되었다. 이 정점은 수 m 높이의 얕은 둔덕들이 무인잠수정에 부착된 비디오 카메라에 의해서 관찰되었다.이곳에서 채취된 길이 약40 cm의 푸쉬코어는 생물교란된 뻘질 퇴적물로 구성되어 있으며, 가스하이드레이트와 chemosynthetic community는 관찰되지 않았다. 푸쉬코어는 X-ray fluorescence scanner를 사용하여 퇴적물의 26가지 원소 조성을 분석하였다. UBGH1-10 정점의 산화환원환경은 Mo/Al과 Mn/Ti 원소비를 이용하여 천부 가스하이드레이트가 발견되지 않은 UBGH1-9와 UBGH1-1 정점과 대비하였다. 이 정점의 일차생산력은 Ba/Al 원소비를 이용하여 다른 정점과 대비하였다. 천부 가스하이드레이트가 발견된 UBGH1-10 정점은 활발한 가스방출과 관련된 생물집단 서식 또는 자생광물 형성의 흔적이 발견되지 않으며, 퇴적물에서도 산화환원환경과 일차생산력의 큰 차이가 관찰되지 않는다.

• Journal of the Korean Magnetics Society
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• v.25 no.1
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• pp.10-15
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• 2015

The model for the magneto-impedance of composite wires composed of highly conductive nonmagnetic metal core and soft magnetic shell was derived based on the Maxwell's equations. The Cu($100{\mu}m$ diameter)/$Ni_{80}Fe_{20}$($15{\mu}m$ thickness) core/shell composite wire was fabricated by electrodeposition. The impedance spectra for the $Cu/Ni_{80}Fe_{20}$ core/shell composite wire were measured in the frequency range of 10 kHz~10 MHz under longitudinal dc magnetic field in 0 Oe~200 Oe. The spectra of complex permeability in circumferential direction were extracted from the impedance spectra by using the derived model. The extracted spectra of complex permeability showed relaxation-type dispersion which is well curve-fitted with Debye equation with single relaxation frequency. By analyzing the magnetic field dependence of the complex permeability spectra, it has been verified that the composite wire has magnetic anisotropy in longitudinal direction and the origin of the single relaxation process is the magnetization rotation in circumferential direction.

• Journal of the Korea Society of Computer and Information
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• v.15 no.11
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• pp.1-9
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• 2010

As the process technology scales down, an interconnection has became a major performance constraint for multi-core processors. Recently, in order to mitigate the performance bottleneck of the interconnection for multi-core processors, a 3D integration technique has drawn quite attention. The 3D integrated multi-core processor has advantage for reducing global wire length, resulting in a performance improvement. However, it causes serious thermal problems due to increased power density. For this reason, to design efficient 3D multi-core processors, thermal-aware design techniques should be considered. In this paper, we analyze the temperature on the 3D multi-core processors in function unit level through various experiments. We also present temperature characteristics by varying application features, cooling characteristics, and frequency levels on 3D multi-core processors. According to our experimental results, following two rules should be obeyed for thermal-aware 3D processor design. First, to optimize the thermal profile of cores, the core with higher cooling efficiency should be clocked at a higher frequency. Second, to lower the temperature of cores, a workload with higher thermal impact should be assigned to the core with higher cooling efficiency.

• The KIPS Transactions:PartA
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• v.17A no.6
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• pp.265-274
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• 2010

As the process technology scales down and integration densities continue to increase, interconnection has become one of the most important factors in performance of recent multi-core processors. Recently, to reduce the delay due to interconnection, 3D architecture has been adopted in designing multi-core processors. In 3D multi-core processors, multiple cores are stacked vertically and each core on different layers are connected by direct vertical TSVs(through-silicon vias). Compared to 2D multi-core architecture, 3D multi-core architecture reduces wire length significantly, leading to decreased interconnection delay and lower power consumption. Despite the benefits mentioned above, 3D design technique cannot be practical without proper solutions for hotspots due to high temperature. In this paper, we propose three floorplan schemes for reducing the peak temperature in 3D multi-core processors. According to our simulation results, the proposed floorplan schemes are expected to mitigate the thermal problems of 3D multi-core processors efficiently, resulting in improved reliability. Moreover, processor performance improves by reducing the performance degradation due to DTM techniques. Power consumption also can be reduced by decreased temperature and reduced execution time.

• Journal of the Korea Society of Computer and Information
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• v.17 no.6
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• pp.1-11
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• 2012

As the process technology scales down, multi-core processors cause serious problems such as increased interconnection delay, high power consumption and thermal problems. To solve the problems in 2D multi-core processors, researchers have focused on the 3D multi-core processor architecture. Compared to the 2D multi-core processor, the 3D multi-core processor decreases interconnection delay by reducing wire length significantly, since each core on different layers is connected using vertical through-silicon via(TSV). However, the power density in the 3D multi-core processor is increased dramatically compared to that in the 2D multi-core processor, because multiple cores are stacked vertically. Unfortunately, increased power density causes thermal problems, resulting in high cooling cost, negative impact on the reliability. Therefore, temperature should be considered together with performance in designing 3D multi-core processors. In this work, we analyze the temperature of the cache in quad-core processors varying cache organization. Then, we propose the low-temperature cache organization to overcome the thermal problems. Our evaluation shows that peak temperature of the instruction cache is lower than threshold. The peak temperature of the data cache is higher than threshold when the cache is composed of many ways. According to the results, our proposed cache organization not only efficiently reduces the peak temperature but also reduces the performance degradation for 3D quad-core processors.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.9
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• pp.97-106
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• 2004

A new test strategy for embedded SOC test is proposed. The SOC test is evaluated by the degree that is the amount of the total reduced test time. Since the test time for a embedded core is determined by the configuration of test wrapper, the total test time is decided by the length of the largest TAM used by the test wrapper. So the DFT(Design for Test) must be involved in the design flow. And the efficient test strategy must be settled. The all Previous test strategies are the methods that find a sub-optimal configurations of scan-chains to minimize the test time after the total TAM lines are divided into a few groups. But this is the NP-complete problem so that all attempts which examine such a TAM configuration and scan-chain division are impossible. In this thesis, a new methodology for this problem is proposed and the efficiency of the methodology is proved.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.10
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• pp.42-50
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• 2000

We show that both cross and bar states with high extinction ratios larger than 30dB can be achieved at eh same ends of ultra-short fused vertical directional coupler switches with two sections by changing the refractive indices of cores and inner cladding layers less than 1%. Based on the calculation of extinction ratios of cross state and bar state for various refractive index and thickness of inner cladding layer and core using the improved coupled mode theory and beam propagation method, the guidelines for design to achieve large tolerances in refractive indices of core and inner cladding layer in fused vertical directional coupler switches are presented.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.5
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• pp.31-40
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• 2002

We propose a novel ultra-short asymmetric vertical directional coupler switch (VDCS) with high extinction ratios larger than 30㏈ composed of switching operation induced section (SOIS), extinction ratio adjusted section (ERAS), and extinction ratio enhanced section (ERES). In this VDCSs, switching operation is achieved by changing the refractive index of one core in SOIS. The improvement of extinction ratios larger than 30㏈ for both cross and bar states is achieved by controlling the asymmetry of refractive indices between both cores in ERES. After propagating through ERAS with symmetry in the structure, different extinction ratios between cross and bar states at the end of SOIS are changed to the same value. For this reason, the optimum asymmetry of the refractive indices of cores to have the maximum extinction ratios and the lengths of ERES are the same for cross and bar states. Design guidelines to achieve high extinction ratios with large tolerances are presented.