• KIPS Transactions on Software and Data Engineering
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• v.7 no.7
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• pp.249-258
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• 2018

The importance of software in military weapon systems is increasing, and the software structure is becoming more complicated. We therefore must thoroughly verify its reliability. In particular, the defects from the interaction of the software components that make up the weapon system are difficult to prevent only with static testing and code coverage level dynamic testing. In this paper, we classify dynamic software defect types and analyze the issues reported in the Open Source Software (OSS) used in the US department of defense weapon systems. The dynamic defects classified in this paper usually occur after integration, and it is difficult to reproduce and identify the cause. Based on this analysis, we come to the point that the software integration test must be enhanced in order to verify the reliability of the weapon system.

• Journal of the Korean Institute of Intelligent Systems
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• v.10 no.5
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• pp.409-416
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• 2000

In the shared-memory mutiprocessor systems, shared processing techniques such as time-sharing, space¬sharing, and gang-scheduling are used to improve the overall system utilization for the parallel operations. Recently, LLPC(Loop-Level Process Control) allocation technique was proposed. It dynamically adjusts the needed number of processors for the execution of the parallel code portions based on the current system load in the given job. This method allocates as many available processors as possible, and does not save any processors for the parallel sections of other later-arriving applications. To solve this problem, in this paper, we propose a new processor allocation technique called FPA(Fuzzy Processor Allocation) that dynamically adjusts the number of processors by fuzzifYing the amounts ofueeded number of processors, loads, and estimated execution times of job. The proposed method provides the maximum possibility of the parallism of each job without system overload. We compare the performances of our approaches with the conventional results. The experiments show that the proposed method provides a better performance.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.20 no.6
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• pp.33-39
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• 2020

Developers spend considerable time manually repairing code that was not built during project construction. If the build fails, it is necessary to understand the failed execution, identify the cause of the failure, and then implement the solution. Build tools such as Gradle have been developed to reduce this effort and automate project construction. However, build tools still do not solve many errors, requiring developers to try to solve build errors. In this study, we propose a solution recommendation method to increase the success rate of Gradle build and reduce the effort required to resolve errors. We provide a way to collect build errors and a way to transition from build error messages to successful builds. In particular, 296 build error messages collected from Github's Java project are classified as solutions, and 89% show that the solution can be applied.

• Journal of Korea Society of Industrial Information Systems
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• v.11 no.4
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• pp.72-81
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• 2006

In this paper, we first define a total of 64 instructions that are considered to be essential and frequently used, construct a datapath diagram, determine the control sequence using a finite state machine, and implement an 8-bit microcontroller using FPGA in VHDL. In the past, only functional simulation results of a rudimentary microcontroller were reported, the microcontroller lacked interrupt handling capability, or it was not implemented in hardware. We have designed a self-contained 8-bit microcontroller such that it can perform data transfer, addition, and logical operations, as well as stack and external interrupt operations. Following timing simulation of the designed microcontroller, we implemented it in an FPGA and verified its operation successfully. The design and implementation has been done under the Altera MAX+PLUS II integrated development environment using the EP1K50TC144-3 chip. The maximum operating frequency, the total number of logic elements used, and the logic utilization were found to be 9.39 MHz, 2813, and 97%, respectively. The result can be used as a microcontroller IP, and as needs arise, the VHDL code can be modified accordingly.

• Journal of KIISE:Computer Systems and Theory
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• v.31 no.1_2
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• pp.125-134
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• 2004

Recently, an on-chip compressed cache system was presented to alleviate the processor-memory Performance gap by reducing on-chip cache miss rate and expanding memory bandwidth. This research Presents an extended on-chip compressed cache system which also significantly expands main memory capacity. Several techniques are attempted to expand main memory capacity, on-chip cache capacity, and memory bandwidth as well as reduce decompression time and metadata size. To evaluate the performance of our proposed system over existing systems, we use execution-driven simulation method by modifying a superscalar microprocessor simulator. Our experimental methodology has higher accuracy than previous trace-driven simulation method. The simulation results show that our proposed system reduces execution time by 4-23% compared with conventional memory system without considering the benefits obtained from main memory expansion. The expansion rates of data and code areas of main memory are 57-120% and 27-36%, respectively.