• Proceedings of the KSME Conference
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• 2005.11a
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• pp.123.1-123.1
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• 2005

• Journal of the Computational Structural Engineering Institute of Korea
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• v.14 no.3
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• pp.309-315
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• 2001

The Stress intensity factors for edge cracks located at the bonding interface between the elastic semiconductor chip and the viscoelastic adhesive layer have been investigated. Such cracks might be generated due to stress singularity in the vicinity of the free surface. The domain boundary element method(BEM) has been employed to investigate the behavior of interface stresses. The overall stress intensity factor for the case of a small interfacial edge crack has been computed. The magnitude of stress intensity factors decrease with time due to viscoelastic relaxation.

• Journal of the Microelectronics and Packaging Society
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• v.8 no.3
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• pp.25-30
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• 2001

The stress intensity factors for edge cracks located at the bonding interface between the semiconductor chip and the adhesive layer subjected to a uniform transverse tensile strain are investigated. Such cracks might be generated due to a stress singularity in the vicinity of the free surface. The boundary element method (BEM) is employed to investigate the behavior of interface stresses. The amplitude of complex stress intensity factor depends on the crack length, but it has a constant value at large crack lengths. The rapid propagation of interface crack is expected if the transverse tensile strain reaches a critical value.

• Proceedings of the Korean Society Of Semiconductor Equipment Technology
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• 2002.11a
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• pp.64-68
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• 2002

플립칩 공정에서는 반도체 칩과 기판사이의 열팽창계수(CTE : Coefficient of Thermal Expansion)의 차와 외적 충격과 같은 이유로 인해 피로균열(Fatigue crack)이나 치명적인 전기적 결함이 발생하게 된다. 이런 부정적인 요인들로부터 칩을 보호하고 신뢰성을 향상시키기 위해서 플립칩 언더필 공정이 적용되고 있다. 본 연구에서는 기존의 몰딩 공정을 응용한 플립칩 언디필 방법을 소개하였다. 공정 이론과 디바이스를 소개하였으며, 시뮬레이션 및 수식을 통하여 최적의 언더필을 위한 몰더 설계 조건을 구하였다. 그리고 본 연구를 통해 기대되는 공정의 장점을 제시하였다.

• Journal of the Microelectronics and Packaging Society
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• v.25 no.1
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• pp.1-10
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• 2018

Recently, there has been rapid development in the field of flexible electronic devices, such as organic light emitting diodes (OLEDs), organic solar cells and flexible sensors. Encapsulation process is added to protect the flexible electronic devices from exposure to oxygen and moisture in the air. Using numerical simulation, we investigated the effects of the encapsulation layer on mechanical stability of the silicon chip, especially the fracture performance of center crack in multi-layer package for various loading condition. The multi-layer package is categorized in two type - a wide chip model in which the chip has a large width and encapsulation layer covers only the chip, and a narrow chip model in which the chip covers both the substrate and the chip with smaller width than the substrate. In the wide chip model where the external load acts directly on the chip, the encapsulation layer with high stiffness enhanced the crack resistance of the film chip as the thickness of the encapsulation layer increased regardless of loading conditions. In contrast, the encapsulation layer with high stiffness reduced the crack resistance of the film chip in the narrow chip model for the case of external tensile strain loading. This is because the external load is transferred to the chip through the encapsulation layer and the small load acts on the chip for the weak encapsulation layer in the narrow chip model. When the bending moment acts on the narrow model, thin encapsulation layer and thick encapsulation layer show the opposite results since the neutral axis is moving toward the chip with a crack and load acting on chip decreases consequently as the thickness of encapsulation layer increases. The present study is expected to provide practical design guidance to enhance the durability and fracture performance of the silicon chip in the multilayer package with encapsulation layer.

• Journal of the Microelectronics and Packaging Society
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• v.14 no.4
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• pp.9-14
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• 2007

In this study, the thermal reliability on flip chip package with non-conductive pastes (NCPs) was evaluated under accelerated conditions. As the number of thermal shock cycle and the dwell time of temperature and humidity condition increased, the electrical resistance of the flip chip package with NCPs increased. These phenomenon was occurred by the crack between Au bump and Au bump and the delamination between chip or substrate and NCPs during the thermal shock and temperature and humidity tests. And the variation of electrical resistance during temperature and humidity test was larger than that during thermal shock test. Therefore it was identified that the flip chip package with NCPs was sensitive to environment with moisture.

• Proceedings of the Korea Concrete Institute Conference
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• 2008.11a
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• pp.677-680
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• 2008

The autogenous shrinkage of HPC is important in that it can lead the early cracks in concrete structures. The purpose of the present study is to explore the autogenous shrinkage of HPC with cellulose fiber and expansive additive and to derive a realistic equation to estimate the autogenous shrinkage model of that. For this purpose, comprehensive experimental program has been set up to observe the autogenous shrinkage for various test series. Major test variables were the quantity of expansive additive and cellulose fiber. Water-cement ratio is fixed with 13%. The autogenous shrinkage of HPC is found to decrease with increasing expansive additive and cellulose fiber. A prediction equation to estimate the autogenous shrinkage of HPC was derived and proposed in this study. The proposed equation shows reasonably good correlation with test data on autogenous shrinkage of HPC.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.16 no.9
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• pp.5748-5755
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• 2015

Scribing is cutting process to determine production amount and characteristic of LED chip. So it is an important process for fabrication of LED chip. Mechanical process and conventional scribing process with laser source has several problems such as thermal deformation, decreasing of material strength and limitation of cutting region. To solve these problems, internal laser scribing process that generates void in wafer and derives self-crack has been researched. However, studies of sapphire wafer cutting by internal laser scribing process for fabrication of LED chip are still insufficient. In this paper, cutting parameters were determined to apply internal laser scribing process for sapphire wafer for fabrication of LED chip. Then, foundation of cutting condition was established to set up internal laser scribing system through investigation of cutting characteristics by several experiments.

• Journal of the Microelectronics and Packaging Society
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• v.7 no.4
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• pp.31-35
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• 2000

The stress state developed in a thin adhesive layer bonded between the semiconductor chip and the leadframe and subjected to a shear loading is investigated. The boundary element method (BEM) is employed to investigate the behavior of interface stresses. Within the context of a linear elastic theory, a stress singularity of type $\gamma^{\lambda=1}$(0<1<1) exists at the point where the interface between one of the rigid adherends and the adhesive layer intersects the free surface. Such singularity might lead to edge crack or delamination.

• Journal of Welding and Joining
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• v.6 no.1
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• pp.35-45
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• 1988

오-스테나이트계 스테인레스강에 대한 용접은 용접재료의 개발과 더불어 각종 산업계에 널리 이용되고 있으며 최근 Type 303 오-스테나이트계 스테인레스강 등은 free machining재로써 널리 응용되고 있다. 그러나 이 303계는 피삭성, 절삭성, 칩형성개선을 위한 특수원소(Se, S 등)의 첨가 때문에 용접성에 문제점을 제기하고 있다. 본 연구에서는 Type 303을 중심으로 AISI 304-316NG 및 347NG계의 오-스테나이트계 스테인레스강의 고온연성거동과 고온균열감수성(용접성)에 관한 연구에 대한 검토중 고온연성거동에 관하여 조사하였다. 고온연성평가는 Gleeble Simulator에 의하여 재료와 방향성에 따라 검토하였으며, 그 결과 모든 재료는 압연방향을 종방으로 시험하였을 때는 거의 유사한 고온연성을 나타내었으나 횡방향으로 시험하였을 때는 종방향에 비하여 연성저하를 나타내었다. 이와 같은 고온연성은 후속연구에서 검토될 고온균열 감수성과 밀접한 관련성에 의하여 용접성을 평가할 수 있다.