• Transactions of the Korean Society of Mechanical Engineers A
• /
• v.36 no.5
• /
• pp.475-479
• /
• 2012

We present a novel polymer fabrication process involving direct UV patterning of a hyperbranched polymer, AEO3000. Compared to PDMS, which is the most widely used polymer in bioMEMS devices, the present polymer has advantages with regard to electrode integration and fast fabrication. We designed a four-chip microelectrofluidic bench having three electrical pads and two fluidic I/O ports. We integrated a microfluidic mixer and a cell separator on the bench to characterize the interconnection performance and sample manipulation. Electrical and fluidic characterization of the microfluidic bench was performed. The measured electrical contact resistance was $0.75{\pm}0.44{\Omega}$, which is small enough for electrical applications, and the pressure drop was 8.3 kPa, which was 39.3% of the value in the tubing method. By performing yeast mixing and a separation test in the integrated module on the bench, we successfully showed that the interconnected chips could be used for bio-sample manipulation.

• Journal of the Microelectronics and Packaging Society
• /
• v.26 no.2
• /
• pp.31-43
• /
• 2019

In this study, polymer elastic bumps were fabricated for the flexible electronic package flip chip bonding and the viscoelastic and viscoplastic behavior of the polymer elastic bumps according to the temperature and load were analyzed using FEM and experiments. The polymer elastic bump is easy to deform by the bonding load, and it is confirmed that the bump height flatness problem is easily compensated and the stress concentration on thin chip is reduced remarkably. We also develop a spiral cap type and spoke cap type polymer elastic bump of $200{\mu}m$ diameter to complement Au metal cap crack phenomenon caused by excessive deformation of polymer elastic bump. The proposed polymer elastic bumps could reduce stress of metal wiring during bump deformation compared to metal cap bump, which is completely covered with metal wiring because the metal wiring on these bumps is partially patterned and easily deformable pattern. The spoke cap bump shows the lowest stress concentration in the metal wiring while maintaining the low contact resistance because the contact area between bump and pad was wider than that of the spiral cap bump.

• Journal of the Microelectronics and Packaging Society
• /
• v.17 no.2
• /
• pp.55-61
• /
• 2010

The device with tantalum silicide heater were bonded by Ag paste and Au SBB(Stud Bump Bonding) onto the Au coated substrate. The shear test after Au ABB and the thermal performance under current stressing were measured. The optimum condition of Au SBB was determined by fractured surface after die shear test and $350^{\circ}C$ for substrate, $250^{\circ}C$ for die during flip chip bonding with bonding load of about 300 g/bump. With applying 5W through heater on the device, the maximum temperature with Ag paste bonding was about $50^{\circ}C$. That with Au SBB on Au coated Si substrate showed $64^{\circ}C$. The difference of maximum temperatures is only $14^{\circ}C$, even though the difference of contact area between Ag paste bonding and Au SBB is by about 300 times and the simulation showed that the contact resistance might be one of the reasons.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2013.02a
• /
• pp.361-361
• /
• 2013

비냉각 적외선 검출소자는 빛이 전혀 없는 환경에서도 사물을 감지하는 열상장비의 핵심소자이다. 마이크로볼로미터 적외선 검출기는 상온에서 동작하며, 온도안정화를 위해 TEC를 장착하여 진공패키지로 조립된다. 패키지는 진공을 유지할 수 있도록 일반적으로 메탈로 제작되며, 단가 감소 및 생산성 증대를 위해 wafer level packaging 방법을 이용한다. 마이크로볼로미터의 특성은 패키지의 진공 변화에 매우 민감하다. 센서의 감도를 증가시키기 위해서는 진공환경을 유지해야 한다. 볼로미터 소자의 특성은 상압에서 열전도는 기판과 멤브레인 사이의 에어갭을 통해 열손실을 야기하므로 센서의 반응도가 현저히 줄어든다. 에어갭이 1 um 정도 되더라도 그 사이에 존재하는 열전도가 가능하므로 진공을 유지하여 열고립 상태를 증대시킬 수 있다. 이에 본 연구에서는 소자의 동작시 압력, 즉 진공도가 볼로미터 소자의 반응도 특성에 미치는 영향을 조사하였다. 마이크로볼로미터 소자는 $2{\times}8$ 어레이 형태로 제작하였으며, metal pad를 각 단위셀에 배치하였으며, 공통전극으로 한 개의 metal pad를 넣어 설계하였다. 흡수체로써 VOx를 사용하였으며, 열 고립구조를 위해 2.5 um 공명 흡수층의 floating 구조로 멤브레인을 형성하였다. 진공패키지는 메탈패키지를 제작하여 볼로미터 칩을 TEC 위에 장착하였으며, 신호의 감지를 위해 가변저항을 매칭시켰다. 반응도는 신호 대 잡음 값을 획득하여 소자에 도달하는 적외선 에너지에 대해 반응하는 값을 계산에 의해 얻어내는 것이다. 픽셀 크기는 $50{\times}50$ um이며, 패키지 조립 공정 후 온도변화에 따른 저항 측정을 통해 TCR 값을 얻었다. 이때 TCR은 약 -2.5%/K으로 나타났다. $2{\times}8$의 4개 단위소자에 대해 측정한 값은 균일하게 TCR 값이 나타났다. 광반응 특성은 볼로미터 단위소자에 대해서 먼저 고진공(5e-6 torr) 하에서 측정하였으며, 반응도는 25,000 V/W의 값을 나타내었고, 탐지도는 약 2e+8 $cmHz_{1/2}$/W로 나타났다. 패키지의 압력 조절을 위해 TMP 및 로터리 펌프를 이용하여 100 torr에서 1e-4 torr의 범위에서 압력조절 밸브를 이용하여 질소가스의 압력으로 진공도를 변화시켰다. 적외선 반응신호는 압력이 증가함에 따라 감소하였으며, 2e-1 torr의 압력에서 신호의 크기가 감소하기 시작하여 5 torr에서 반응도의 1/2 값을 나타냄을 알 수 있었다. 30 torr 이상에서는 신호가 잡음값 과거의 동일하여 신호대 잡음비가 1로 나타남을 알 수 있었다. 또한 진공도 변화에 대해, 흑체온도에 따른 반응도 및 탐지도의 특성을 조사한 결과를 발표한다. 반응도의 증가를 위해 진공도는 진공도는 1e-2 torr 이하의 압력을 유지해야 함을 본 실험을 통해 알 수 있었다.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
• /
• v.13 no.5
• /
• pp.359-369
• /
• 2020

In this paper, we proposed a charge pump (CP) circuit that has a wide operating range while reducing the current mismatch for the PLL that generates the main clock of the CMOS X-Ray detector. The operating range and current mismatch of the CP circuit are determined by the characteristics of the current source circuit for the CP circuit. The proposed CP circuit is implemented with a wide operating current mirror bias circuit to secure a wide operating range and a cascode structure with a large output resistance to reduce current mismatch. The proposed wide operating range cascode CP circuit was fabricated as a chip using a 350nm CMOS process, and current matching characteristics were measured using a source measurement unit. At this time, the power supply voltage was 3.3 V and the CP circuit current ICP = 100 ㎂. The operating range of the proposed CP circuit is △VO_Swing=2.7V, and the maximum current mismatch is 5.15 % and the maximum current deviation is 2.64 %. The proposed CP circuit has low current mismatch characteristics and can cope with a wide frequency range, so it can be applied to systems requiring various clock speed.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.12 no.7
• /
• pp.1227-1234
• /
• 2008

In this paper is designed a 256-bit synchronous OTP(one-time programmable) memory required in application fields such as automobile appliance power ICs, display ICs, and CMOS image sensors. A 256-bit synchronous memory cell consists of NMOS capacitor as antifuse and access transistor without a high-voltage blocking transistor. A gate bias voltage circuit for the additional blocking transistor is removed since logic supply voltage VDD(=1.5V) and external program voltage VPPE(=5.5V) are used instead of conventional three supply voltages. And loading current of cell to be programmed increases according to RON(on resistance) of the antifuse and process variation in case of the voltage driving without current constraint in programming. Therefore, there is a problem that program voltage can be increased relatively due to resistive voltage drop on supply voltage VPP. And so loading current can be made to flow constantly by using the current driving method instead of the voltage driving counterpart in programming. Therefore, program voltage VPP can be lowered from 5.9V to 5.5V when measurement is done on the manufactured wafer. And the sens amplifier circuit is simplified by using the sens amplifier of clocked inverter type instead of the conventional current sent amplifier. The synchronous OTP of 256 bits is designed with Magnachip $0.13{\mu}m$ CMOS process. The layout area if $298.4{\times}314{\mu}m2$.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.41 no.2
• /
• pp.47-54
• /
• 2004

Up to the present, there have been many works to analyze interconnects on timing aspects, while less works have been done on power aspects. As resistance of interconnects and rise time of signals increase, power consumption associated with interconnects is ever-increasing. In case of clock trees, particularly power consumption associated with interconnects is over 30％ of total power consumption. Hence, an efficient method to compute power consumption of interconnects is necessary and in this paper we propose a simple yet accurate method to estimate dynamic power consumption of interconnects. We propose a new reduced-order model to estimate power consumption of large interconnects. Through the proposed model which is directly derived from total capacitance and resistance of interconnects, we show that the dynamic power consumption of whole interconnects can be approximated, and propose an analytical method to compute the power consumption. The results applying the proposed method to various RC networks show that average relative error is 1.86％ and maximum relative error is 9.82％ in comparison with HSPICE results.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.20 no.10
• /
• pp.1084-1090
• /
• 2009

This paper presents a balun consisting of a T-junction, a Right/Left Handed Transmission line(RLH-TL), and a conventional Right Handed(RH) line. It is assumed that the RLH-TL consists of N unit-cells. We provide closed-form solutions and design a very compact wideband(80 %) balun using CPW lines based on the obtained solutions. Then, we propose a capacitively loaded loop antenna designed for a uniform current distribution. The antenna resistance of the proposed antenna at resonance is about 204 ohms. The length of the unit cell is about $\lambda/12$(total length: $1\;\lambda$). The magnetic field generated from the proposed antenna is stronger than that of the conventional one by as much as 20 dB. We used a coplanar strip line(CPS) to combine the loop antenna and balun. The proposed antenna may be used as a near field UHF RFID reader antenna.

• Journal of Sensor Science and Technology
• /
• v.8 no.1
• /
• pp.69-79
• /
• 1999

The research and implementation was preformed on high-resolution CCTV camera with CCD exclusive DSP conventional analog signal processor CCTV camera has its limit on auto exposure(AE), auto white balance(AWB), back light compensation(BLC) processing, severe distortion and noise of image, manual control parameter setting, etc. In our study, to resolve the problems in conventional CCTV camera, we made it possible to control AE, AWB, BLC automatically by the use of the DSP, which are used exclusively in the CCD camera produced domestically, and the microcontroller. And we utilized the function of screen display of microcontroller for the user-friendly interface to control CCD camera. And the electronic variable resister(EVR) was used to avoid setting parameters manually in the level of manufacturing process. As the result, It became possible to control parameters of the camera by program. And the cost-down effect was accomplished by improving the reliability of parameter values and reducing the efforts in setting parameters.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2013.02a
• /
• pp.344-344
• /
• 2013

칩의 크기가 감소함에 따라 RC (Resistance, Capacitance) 지연, 전력소비증가 및 신호잡음 등이 문제가 되어왔다. RC지연 문제는 배선에 알루미늄 보다 비저항이 낮은 구리를 사용하고 절연막으로 유전상수가 낮은 물질을 사용하여 개선될 수 있다. 이와 같은 맥락에서 점차 저유전상수 박막의 필요성은 증가하고 있다. 그러므로 이를 개선하기 위해 저 유전상수 값을 가지는 물질을 개발 혹은, UV나 플라즈마 그리고 열을 이용하여 처리하는 연구가 절실히 요구되고 있으며, 현재 많은 연구가 진행되고 있다. 이 논문에서 저유전박막은 HDP-CVD (High Density Plasma Chemical Vapor Deposition) 시스템에서 (CyOz)-SiHx와 O2의 비율을 각각 변화시키면서 증착 되었다. (CyOz)-SiHx와 O2의 비율은 60/150, 60/180, 60/210, 60/240로 증가하면서 증착하였다. 그리고 surface profilometer을 이용하여 박막의 증착율을 측정하고 LCR meter를 이용하여 정전용량을 측정하여 유전상수 값을 얻었다. 박막의 화학적 조성과 구조는 FTIR (Fourier Transform Infrared Spectroscopy)로 측정하였다. 박막의 유동 특성은 SEM (Scanning electron microscope) 이미지로 살펴보았다.