• Journal of the Institute of Electronics Engineers of Korea SC
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• v.39 no.4
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• pp.25-35
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• 2002

This work describes an 8b 200MHz time-interleaved subranging analog-to-digital converter (ADC) based on a single-poly digital CMOS process. Two fine ADCs for lower digital bits of the proposed ADC employ a time-sharing double-channel architecture to increase system speed and a new reference voltage switching scheme to reduce settling time of the reference voltages and chip area. The proposed intermeshed resistor string, which generates reference voltages for fine ADCs, improves linearity and settling time of the reference voltages simultaneously. The proposed sample- and-hold amplifier(SHA) is based on a highly linear common-drain amplifier and passive differential circuits to minimize power consumption and chip area with 8b accuracy and employs input dynamic common mode feedback circuits for high dynamic performance at a 200MHz sampling rate. A new encoding circuit in a coarse ADC simplifies the signal processing between the coarse ADC and two successive fine ADCs.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.7
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• pp.1-9
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• 2011

Memristor is a portmanteau of "memory resistor". The resistance of memristor is changed depends on the history of electric charge that passed through the device and it is able to memorize the last resistance after turning off the power supply. This paper presents this device that has a high chance to be the next generation of commercial non-volatile memory and its behavior modeling using SPICE simulation. The memristor MOS content addressable memory (M_CAM) is also designed and simulated using the proposed behavioral model. The proposed M_CAM unit cell area and power consumption show an improvement around 40% and 96%, respectively, compare to the conventional SRAM based CAMs. The M_CAM layout is also implemented using 0.13${\mu}m$ mixed-signal CMOS process under 1.2 V supply voltage.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.05a
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• pp.349-351
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• 2013

This research paper presents a low-power programmable gain amplifier (PGA) to facilitate signal processing of the detection of defects in steel plates. This circuit is able to adjust a gain in the range of 6 to 60dB in 7 steps using different signal types for various defects from hall sensors. The gain of PGA is designed by operating on-resistors of switches and passive components. The proposed PGA ($0.18{\mu}m$ CMOS process with 1.8 supply voltage) showed excellent gain error of less than -0.2dB, and low power consumption of 0.47mW.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.9
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• pp.82-90
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• 2014

In this paper, a couple of 4-channel differential transimpedance amplifier arrays are realized in a standard 0.18um CMOS technology for the applications of linear LADAR(laser detection and ranging) systems. Each array targets 1.25-Gb/s operations, where the current-mode chip consists of current-mirror input stage, a single-to-differential amplifier, and an output buffer. The input stage exploits the local feedback current-mirror configuration for low input resistance and low noise characteristics. Measurements demonstrate that each channel achieves $69-dB{\Omega}$ transimpedance gain, 2.2-GHz bandwidth, 21.5-pA/sqrt(Hz) average noise current spectral density (corresponding to the optical sensitivity of -20.5-dBm), and the 4-channel total power dissipation of 147.6-mW from a single 1.8-V supply. The measured eye-diagrams confirms wide and clear eye-openings for 1.25-Gb/s operations. Meanwhile, the voltage-mode chip consists of inverter input stage for low noise characteristics, a single-to-differential amplifier, and an output buffer. Test chips reveal that each channel achieves $73-dB{\Omega}$ transimpedance gain, 1.1-GHz bandwidth, 13.2-pA/sqrt(Hz) average noise current spectral density (corresponding to the optical sensitivity of -22.8-dBm), and the 4-channel total power dissipation of 138.4-mW from a single 1.8-V supply. The measured eye-diagrams confirms wide and clear eye-openings for 1.25-Gb/s operations.

• Korean Journal of Plant Resources
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• v.16 no.3
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• pp.264-274
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• 2003

Many potato genetic resources have been collected and improved for their diverse traits over the years using breeding program in KPGR. To select potential varieties for table and processing in Korea, 58 elite potato breeding lines and several 'Valley' varieties were cultivated and harvested at Korea Alpine area in 2001. The cultivated lines and varieties were evaluated using their cultural adaptability in the environment and tuber characteristics, such as the depth of tuber eye, tuber shape, skin color, flesh color, scab resistance, yield, and the resistance of hollow heart and internal brown spot disease. Additionally, in the selection of potential processing varieties, reducing sugar content (sum of glucose and fructose concentration) of tubers is critically considered, because it mainly influence on the chip color of processing potato tuber. For table stock varieties with white skin color, 'Early Valley', 'Summer Valley', 'Winter Valley', and 'Taebok Valley' were selected. In the aspect of diverse potato tuber color, several varieties were selected such as 'Golden Valley' for its yellow fresh and skin color, 'Gogu Valley', 'Juice Valley', and 'Rose Valley' for their red skin color, and 'Purple Valley' for its purple skin. Compared with world wide known processing cultivar 'Atlantic', 24 lines (or varieties) were selected for the potential potato processing industry due to their low reducing sugar contents (below 0.3％), high yield (above 4.0 ton/ha), and unique chip colors. Selected white chipping varieties were 'Taedong Valley', 'Kangshim Valley', and 'Kangwon Valley', which have 0.23％, 0.27％, and 0.29％ of reducing sugar contents, respectively. 'Bora Valley', having deep purple color in both skin and fresh, was selected for purple chip variety and has 0.26％ of reducing sugar content. Light yellow chip varieties (lines) were 'Rose Valley' and Valley 54, having 0.19％ and 0.269％ of reducing sugar content, respectively. For French frying potatoes, 'Stick Valley' of 0.22％ and Valley 72 of 0.151％ in reducing sugars were selected. All of these selected lines and 'Valley' varieties can be used as parents to improve potato genetic resources and to develop better varieties with unique traits and colors.

• Proceedings of the Korean Society of Machine Tool Engineers Conference
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• 2002.04a
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• pp.302-307
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• 2002

In end milling process, the undeformed chip section area and cutting forces vary periodically with phase change of the tool. However, the real undeformed chip section area deviates from the geometrically ideal one owing to cutter runout and tool shape error. In this study, a method of estimating the real undeformed chip section area which reflects cutter runout and tool shape error was presented during up-end milling of Inconel 718 using measured cutting forces. The specific cutting resistance, K. and $K_t$ are defined as the radial and tangential cutting forces divided by the modified chip section area. Both of $K_r$, and $K_t$ values become smaller as the helix angle increases from $30^\circ$ to $40^\circ$ Whereas they become larder as the helix angle increases from $40^\circ$ to $50^\circ$. On the other hand, the $K_r$, and $K_t$ values show a tendency to decrease with increase of the modified chip section area and this tendency becomes distinct with smaller helix angle.

• Proceedings of the Korean Society of Machine Tool Engineers Conference
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• 2002.04a
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• pp.308-313
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• 2002

In end milling process, the undeformed chip section area and cutting forces vary periodically with phase change of the tool. However, the real undeformed chip section area deviates from the geometrically ideal one owing to cutter runout and tool shape error. In this study, a method of estimating the real undeformed chip section area which reflects cutter runout and tool shape error was presented during down end-milling of Inconel 715 using measure cutting forces. Contrary to the up-end milling the value of radial specific cutting resistance, $K_r$, becomes larger as the helix angle increases from $30^{\circ}$ to $40^{\circ}$ and it shows almost same value at $50^{\circ}$ The value of tangential specific cutting resistance, $K_t$ becomes larger as the helix angle increases same as in up-end milling, the $KK_r$, and $K_t$ values show a tendency to decrease with increase of the modified chip section area and this tendency is distinct with helix angle $40^{\circ}$.

• Journal of the Korean Society for Precision Engineering
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• v.18 no.7
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• pp.143-148
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• 2001

In this study, a mechanistic model of cutting force components in up and down end milling process is presented. Using this cutting force model of 4-tooth endmills with various helix angles, cutting force variation of inconel 718 has been predicted. Predicted values of cutting force components are coincide well with the measured ones. As helix angle increases, overlapping effects of the active cutting edges increase. In up endmilling the magnitudes of radial and feed cutting force componts FX and FY are lowest when the helix angle is $40\{\circ}$, but in down endmilling the magnitudes of these values increase slightly as helix angle becomes large.

• Journal of the Korean Society for Precision Engineering
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• v.19 no.8
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• pp.63-70
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• 2002

In end milling process, the undeformed chip section area and cutting forces vary periodically with phase change of the tool. However the real undeformed chip section area deviates from the geometrically ideal one owing to cutter runout and tool shape error. In this study, a method of estimating the real undeformed chip section area which reflects cutter runout and tool shape error was presented in up end milling process using measured cutting forces. The average specific cutting resistance, Ka is defined as the main cutting force component divided by the modified chip section area. Ka value becomes smaller as the helix angle increases from $30^circC \;to\;40\circC$. But it becomes larger as the helix angle increases from $40^\circ$to 50 . On one hand, the Ka value shows a tendency to decrease with increase of the modified chip section area and this tendency becomes distinct with smaller helix angle.

• Journal of Satellite, Information and Communications
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• v.10 no.4
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• pp.1-5
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• 2015

The ESD(electrostatic discharge) protection performance of PPS(PMOS pass structure) embedded N-type silicon controlled rectifier(NSCR_PPS) device with different partial p-well(PPW) structure was discussed for high voltage I/O applications. A conventional NSCR_PPS standard device shows typical SCR-like characteristics with low on-resistance, low snapback holding voltage and low thermal breakdown voltage, which may cause latch-up problem during normal operation. However, our proposed NSCR_PPS devices with modified PPW_PGM(primary gate middle) and optimal CPS(counter pocket source) implant demonstrate the stable ESD protection performance with high latch-up immunity.