• Journal of the Korean Institute of Intelligent Systems
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• v.12 no.3
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• pp.202-209
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• 2002

This paper deals with simplification of classification rules for data mining and rule bases for control systems. Datamining that extracts useful information from such a large amount of data is one of important issues. There are various ways in classification methodologies for data mining such as the decision trees and neural networks, but the result should be explicit and understandable and the classification rules be short and clear. The rough sets theory is an effective technique in extracting knowledge from incomplete and inconsistent data and provides a good solution for classification and approximation by using various attributes effectively This paper investigates granularity of knowledge for reasoning of uncertain concopts by using rough set approximations and uses a hierarchical classification structure that is more effective technique for classification by applying core to upper level. The proposed classification methodology makes analysis of an information system eary and generates minimal classification rules.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.1
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• pp.60-68
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• 2010

In case of sensorineural hearing loss, auditory perception can be activated by electrical stimulation of the nervous system via electrode implanted into the cochlea or auditory nerve. Since the tonotopic map of the human auditory nerve has not been definitively identified, the recording of auditory nerve signal with microelectrode is desirable for determining the tonotopic map. This paper proposes the multi-channel analog front-end for auditory nerve signal detection. A channel of the proposed analog front-end consists of an AC coupling circuit, a low-power 4th-order Gm-C LPF, and a single-slope ADC. The AC coupling circuit transfers only AC signal while it blocks DC signal level. Considering the bandwidth of the auditory signal, the Gm-C LPF is designed with OTAs adopting floating-gate technique. For the channel-parallel ADC structure, the single-slope ADC is used because it occupies the small silicon area. Experimental results shows that the AC coupling circuit and LPF have the bandwidth of 100 Hz - 6.95 kHz and the ADC has the effective resolution of 7.7 bits. The power consumption per a channel is $12\;{\mu}W$, the power supply is 3.0 V, and the core area is $2.6\;mm\;{\times}\;3.7\;mm$. The proposed analog front-end was fabricated in a 1-poly 4-metal $0.35-{\mu}m$ CMOS process.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.11a
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• pp.230-230
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• 2007

전력선 통신(Power Line Communication)은 최근 전력선을 이용한 통신기술의 발달과 더불어 세계적으로 관심도가 높아지고 연구 개발 및 자본 투자가 활발히 진행되고 있으며, 안정적인 네트워크를 구성하기 위해서는 고주파 전력선 통신 신호를 차단하는 블로킹 필터가 반드시 적용되어야 한다. 전력선 통신용 블로킹 필터는 광대역의 주파수 특성과 높은 신호감쇄 특성 및 대전류 특성이 요구되며, 이러한 특성을 구현하기 위해서는 블로킹 필터의 핵심부품인 자심재료의 고투자율 및 대전류화가 이루어져야 한다. 따라서 본 연구에서는 우수한 전 자기적 특성이 균일하게 유지되고, 전력선에 흐르는 대전류에 의한 자심재료의 포화가 발생하지 않도륵 새로운 자심 재료를 설계하여, 전력선 통신을 적용한 홈 네트워크 구축의 핵심 부품인 광대역 블로킹 필터를 개발하고자 하였다. 2350과 0.3 T의 투자율과 포화자속 밀도를 갖는 EI 형상의 자심재료를 해석모델로 설정하고 다중 에어 갭의 위치에 따른 전류와 자속밀도 변화를 유한요소 해석법으로 분석한 결과 자심재료의 대전류 특성에 지배적인 영향을 미치는 에어 캡의 삽입 위치를 알 수 있었고, 새로운 해석 모델인 I 형상의 로드(ROD) 코어에 대해 수치해석을 수행하여, 100A의 통전 전류에서도 자기적으로 포화되지 않고 인덕턴스의 정밀 제어가 가능하고, 특성의 신뢰성과 대전류에 대한 안정성을 증가시킬 수 있는 인덕터를 설계하였다. 또한 수동소자를 이용한 LC 공진회로를 기본 구성으로 하고, 주파수 대역, 신호 감쇄율과 대전류 특성, 상용화를 고려하여 블로킹 필터 회로를 설계하였으며, 유한요소해석법을 적용한 전자장 모의해석을 통하여 최소의 크기를 갖는 I 형상의 자심재료에 $6{\Phi}$의 에나멜 동선을 6.5턴, 6턴 권선하여 2.5, $2.15\;{\mu}H$의 인덕턴스를 갖는 직렬 인덕터를 구현하였고 블로킹 필터를 구성하였다. 주파수에 따른 신호감쇄 특성을 5 Hz~1 MHz의 주파수 범위에서 측정한 결과 약 490 kHz~450 kHz의 주파수 대역에서 -70dB의 신호감쇄 특성을 나타냈다. 본 연구를 통해 개발된 100A급 광대역 블로킹 필터가 적용되어 상용화 될 수 있을 것으로 판단되며, 또한 모뎀 통신 주파수 대역에서 -70dB 이상의 높은 감쇄 특성을 갖기 때문에 신호차단 특성이 보다 우수할 것으로 사료된다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.7
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• pp.1071-1077
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• 2022

A security SoC that can be used to implement elliptic curve cryptography (ECC) based public-key infrastructures was designed. The security SoC has an architecture in which a hardware accelerator for the elliptic curve digital signature algorithm (ECDSA) is interfaced with the Cortex-A53 CPU using the AXI4-Lite bus. The ECDSA hardware accelerator, which consists of a high-performance ECC processor, a SHA3 hash core, a true random number generator (TRNG), a modular multiplier, BRAM, and control FSM, was designed to perform the high-performance computation of ECDSA signature generation and signature verification with minimal CPU control. The security SoC was implemented in the Zynq UltraScale+ MPSoC device to perform hardware-software co-verification, and it was evaluated that the ECDSA signature generation or signature verification can be achieved about 1,000 times per second at a clock frequency of 150 MHz. The ECDSA hardware accelerator was implemented using hardware resources of 74,630 LUTs, 23,356 flip-flops, 32kb BRAM, and 36 DSP blocks.

• Economic and Environmental Geology
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• v.34 no.4
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• pp.355-373
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• 2001

Palaeomagnesim of Paleozoic Tuwibong Type Sequence in Yemi area was studied with a total of 256 core-samples collected from 23 sites. The study area (geographical coordinates: 37.l8$^{\circ}$N, l28.610E) is located between Taebaek and Yongwol belonging to the northeastern part of the Okchon Belt. Thermal cleaning was a most effective method to extract stable characteristic remanent magnetization (ChRM) direction, even though AF cleaning also worked on some specimens. Mean ChRM direction of the Cambrian Hwajol Formation was different from the present-day field direction and showed maximum clustering (max. k value) at 100% bedding-tilt correction. However, it could not pass the fold test. Ordovician Makkol and Kosong Limestones as well as Permian Sadong and Kobangsan Formations have very weak NRM, and were remagnetized into the present-day field direction. ChRM directions from the Carboniferous Hongjom Formation passed both fold and reversal tests. IRM experiments and blocking temperature spectrum indicate that both magnetite and haematite are carrier of the primary magnetization. Palaeomagnetic pole position from the Carboniferous Hongjom Formation is very similar to that of contemporary North China Block (NCB) suggesting that the study area was a part of, or located very near to, the NCB during Carboniferous.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.37 no.6
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• pp.761-768
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• 2013

New warheads are designed and developed to be highly lethal when used as part of ballistic missile payloads. There are many trades associated with the design of a central warhead core, mainly dealing with the projectiles or penetrators. Obviously, a payload-type configuration is very susceptible to kills from one projectile because of the high impacts required for bomblet or submunition payloads. Based on these requirements, the optimum kill vehicle configuration will have the smallest mass and relative velocity that will kill all the submunitions. The designs of the penetrator shape and size are directly related to the space and weight of the warhead. The shape, size, L/D, penetrator material, and manner in which they are inserted inside the surrounding explosive segments are critical in achieving successful penetrator design. The AUTODYN-3D code was used to study the effect of penetrator penetration. The objective of numerical analysis was to determine the penetration characteristics of the penetrator produced by hypervelocity impacts under different initial conditions such as initial velocity, shape, and L/D of the penetrator.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.17 no.4
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• pp.266-274
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• 2024

In this paper, we designed a low-area 32-bit PF (Poly-fuse) OTP IP, a non-volatile memory that stores data required for analog circuit trimming and calibration. Since one OTP cell is constructed using two PFs in one select transistor, a 1cell-2bit multibit PF OTP cell that can program 2bits of data is proposed. The bitcell size of the proposed 1cell-2bit PF OTP cell is 1/2 of 12.69㎛ × 3.48㎛ (=44.161㎛2), reducing the cell area by 33% compared to that of the existing PF OTP cell. In addition, in this paper, a new 1 row × 32 column cell array circuit and core circuit (WL driving circuit, BL driving circuit, BL switch circuit, and DL sense amplifier circuit) are proposed to meet the operation of the proposed multbit cell. The layout size of the 32bit OTP IP using the proposed multibit cell is 238.47㎛ × 156.52㎛ (=0.0373㎛2) is reduced by about 33% compared that of the existing 32bit PF OTP IP using a single bitcell, which is 386.87㎛ × 144.87㎛ (=0.056㎛2). The 32-bit PF OTP IP, designed with 10 years of data retention time in mind, is designed with a minimum programmed PF sensing resistance of 10.5㏀ in the detection read mode and of 5.3 ㏀ in the read mode, respectively, as a result of post-layout simulation of the test chip.