• The KIPS Transactions:PartD
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• v.18D no.3
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• pp.157-168
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• 2011

Recently flash memory has been being utilized as a main storage device in mobile devices, and flashSSDs are getting popularity as a major storage device in laptop and desktop computers, and even in enterprise-level server machines. Unlike HDDs, on flash memory, the overwrite operation is not able to be performed unless it is preceded by the erase operation to the same block. To address this, FTL(Flash memory Translation Layer) is employed on flash memory. Even though the modified data block is overwritten to the same logical address, FTL writes the updated data block to the different physical address from the previous one, mapping the logical address to the new physical address. This enables flash memory to avoid the high block-erase cost. A flashSSD has an array of NAND flash memory packages so it can access one or more flash memory packages in parallel at once. To take advantage of the internal parallelism of flashSSDs, it is beneficial for DBMSs to request I/O operations on sequential logical addresses. However, the B-tree structure, which is a representative index scheme of current relational DBMSs, produces excessive I/O operations in random order when its node structures are updated. Therefore, the original b-tree is not favorable to SSD. In this paper, we propose AS(Always Sequential) B-tree that writes the updated node contiguously to the previously written node in the logical address for every update operation. In the experiments, AS B-tree enhanced 21% of B-tree's insertion performance.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.4
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• pp.727-736
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• 2009

In this paper, the $arccos(cos^{-1})$ arithmetic unit for mobile graphics accelerator is designed. The mobile vector graphics applications need tight area, execution time, power dissipation, and accuracy constraints compared to desktop PC applications. The designed processor adopts 2nd-order polynomial approximation scheme based on IEEE floating point data format to satisfy speed and accuracy conditions and reduces area via hardware sharing structure. The arccosine processor consists of 15,280 gates and its estimated operating frequency is about 125Mhz at operating condition of $0.35{\mu}m$ CMOS technology. Because the processor can execute arccosine function within 7 clock cycles, it has about 17 MOPS(million arccos operations per second) execution rate and can be applicable to mobile OpenVG processor. And because of its flexible architecture, it can be applicable to the various transcendental functions such as exponential, trigonometric and logarithmic functions via replacement of ROM and minor hardware modification.

• Spatial Information Research
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• v.10 no.1
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• pp.61-76
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• 2002

Mobile map services using PDA are prevailing because of the rapid developments of techniques of the internet and handhold devices recently. While the volume of spatial data is tremendous and the spatial operations are time-intensive, the PDA has small size memory and a low performance processor. Therefore, the spatial index for PDA should be small size and efficiently filter out the candidate objects of spatial operation as well. This paper proposes a spatial index far PDA called MHF(Multilevel Hashing File). The MHF has simple structure for storage efficiency and uses a hashing technique, which is direct search method, for search efficiency. This paper also designs a compression technique for MBR. which occupies almost 80% of index data in the two dimensional case. We call it HMBR. Although the HMBR technique reduces the MB\ulcorner size to almost a third, it shows good filtering efficiency because of no information loss by quantization in case of small objects that occupy a major portion. Our experimental tests show that the proposed MHF index using HMBR technique is appropriate for PDA in terms of the size of index, the Number of MBR comparisons, the filtering efficiency and the execution time of spatial operations.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.16 no.3
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• pp.7-12
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• 2016

DRAM is commonly used as a smartphone memory medium, but extending its capacity is challenging due to DRAM's large battery consumption and density limit. Meanwhile, smartphone applications such as social network services need increasingly large memory, resulting in long latency due to additional storage accesses. To alleviate this situation, we adopt emerging nonvolatile memory (NVRAM) as smartphone's buffer cache and propose an efficient management scheme. The proposed scheme stores all dirty data in NVRAM, thereby reducing the number of storage accesses. Moreover, it separately exploits read and write histories of data accesses, leading to more efficient management of volatile and nonvolatile buffer caches, respectively. Trace-driven simulations show that the proposed scheme improves I/O performances significantly.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.10a
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• pp.97-100
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• 2007

In order to overcome many defects in the current JPEG standard of still image compression, the new JPEG2000 standard has been development. The JPEG2000 standard is based on the principles of DWT and EBCOT Entropy Coding. EBCOT(Embedded block coding with optimized truncation) is the most important technology in the latest image-coding standard, JPEG2000. However, EBCOT occupies the highest computation time to operate bit-level processing. Therefore, many researches have achieved methods to minimize computation speed of EBCOT. Thus, this paper proposes the method of context-extraction that improves computational architecture. This paper proposes efficient context coding method. The proposed algorithm would apply to hard-wired JPEG2000 Encoder that is used for compression of high resolution image.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.6C
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• pp.539-546
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• 2010

In next generation wireless communication systems based on OFDM, multiple-input multiple-output (MIMO) technique is adopted in order to achieve high data throughput with limited bandwidth. As one of MIMO techniques, spatial multiplexing scheme needs high performance data detection algorithm that can be performed with low computational complexity. In this paper, we propose an algorithm that can compute QRM-MLD with reduced complexity. Also, hybrid detection technique is proposed, which can reduce the complexity by selecting between MMSE and QRM-MLD according to the channel condition. The proposed algorithm provides the trade-off between performance and complexity. The computer simulations for downlink transmission in 3GPP LTE system show that less than 0.1dB performance degradation can be achieved at 0.1% BER with 59% reduction on computational complexity compared with the conventional QRM-MLD algorithm.

• Education of Primary School Mathematics
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• v.19 no.4
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• pp.313-327
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• 2016

The purpose of this study is to develop the number-operation games and to analyze the effects of the games on mathematical creativity of gifted elementary students. We set up the basic direction and standard of mathematical gifted creativity program and developed the 10 periods games based on the mathematically gifted creative problem solving(MG-CPS) model. And, to find out the change of students' creativity, the test based on the developed program and one group pretest-posttest design was conducted on 20 gifted students. Analysis of data using Leikin's evaluation model of mathematical creativity with Leikin's scoring and categorization frame revealed that gifted students's creativity is improved via the number-operation games.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.26 no.6
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• pp.1431-1441
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• 2016

In case of ARX based block cipher algorithms with masking countermeasures, there is a need for a method to convert between Boolean masking and arithmetic masking. However, to apply masking countermeasures to ARX based algorithms is less efficient compared to masked AES with single masking method because converting between Boolean and arithmetic masking has high computation time. This paper shows performance results on 32-bit platform implementations of LEA with various masking conversion countermeasures against first order side channel attacks. In the implementation point of view, this paper presents computation time comparison between actual measurement value and theoretical one. This paper also confirms that the masked implementations of LEA are secure against first order side channel attacks by using a T-test.

• Education of Primary School Mathematics
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• v.21 no.3
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• pp.289-307
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• 2018

Although mixed calculation of natural numbers is important in that it completes arithmetic calculation of natural numbers in elementary school, few studies have been conducted regarding its instruction methods. Given this, this study analyzed Korean mathematics textbooks (from the fifth textbooks to the 2009 revised textbooks) along with Japanese and Singaporean textbooks in terms of the parentheses and the order of operations regarding mixed calculation of natural numbers. The results of this study showed that there were differences in introducing the parentheses and representing them in an explicit way per textbooks. In the Korean textbooks, the order of operations was presented mostly with the real-life contexts but it was not always in a diagrammatic representation. In contrast, in the Singaporean textbooks, the order of operations was presented without the real-life contexts and the use of calculators was emphasized. In the Japanese textbooks, the order of operations was presented with the real-life contexts and a hierarchy of operations was emphasized. Based on these results, this study suggested several implications of textbook development and instructional methods regarding mixed calculations of natural numbers.

• Proceedings of the Korean Information Science Society Conference
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• 2002.04a
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• pp.862-864
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• 2002

정보 보안을 위한 암호화 처리는 각종 컴퓨터 시스템이나 통신시스템에서 부가적으로 수행되기 때문에암호화 속도가 느린 경우에는 시스템의 속도 지연을 유발시키게 된다. 따라서 고속의 컴퓨터 연산이나 고속통신에 있어서 이에 맞는 고속의 암호화는 필수적으로 해결되어야 할 과제인데, 이것은 암호화 및 복호화를 하드웨어로 처리함으로서 가능하다. 본 연구에서는 차세대 표준 암호화 알고리즘인 AES-128의 암호화와 복호화를 단일 ASIC칩에 구현하고, 인터페이스 핀의 수와 내부 모듈간의 버스 폭에 따른 칩의 효율성을 평가하였다. 이 연구에서 VHDL 설계 및 시뮬레이션은 Altera 사의 MaxPlus 29.64를 이용하였으며, ASIC 칩은 Altera 사의 FLEXIOK 계열의 칩을 사용하였다.