• Title/Summary/Keyword: 차동 변환 모드

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Design of Single-Inductor Dual-Output Boost-Boost DC-DC Converter with Dual Feedback Loop Based on Relative Sawtooth Generator (Dead-time을 갖는 톱니파 발생기를 이용한 이중 피드백 루프 기반 단일 인덕터 이중 출력 승압형 변압기 설계)

  • Yun, Dam;Kim, Dong-Young;Lee, Kang-Yoon
    • Journal of IKEEE
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    • v.18 no.2
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    • pp.220-227
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    • 2014
  • This paper presents a control method of Single-Inductor Dual-Output DC-DC Converter using Common mode feedback and differential feedback loops. To generate duty used for differential mode feedback loop, this paper propose relative sawtooth circuit using current divider circuit which makes ramp signal with variable dead-time. Two outputs of the Single-Inductor Dual-Output DC-DC Converter are specified for 2.8 V and 4.2 V with input voltage 2.5 V. The maximum conversion efficiency of designed SIDO DC-DC Converter is 95% at total output power of 539mW. Cross regulations of Boost1 and Boost2 are 3.57% and 4% each, when increasing twice times output current.

Evaluation of Y-Cap Capacitance in EMI Filter Design Using Measured S-Parameter (측정된 S-파라메터를 이용한 EMI 필터의 Y-캡 용량 산정에 대한 연구)

  • Kim, Jonghyeon;Jeon, Jiwoon;Kim, Taeho;Kim, Sungjun;Nah, Wansoo
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.25 no.3
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    • pp.319-332
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    • 2014
  • Insertion loss is used as the character to express the efficiency of EMI filter. In this paper, we studied the better method that can measure the insertion loss of EMI filter exactly than the original method. For the achievement of this, the method measuring both common mode(CM) and differential mode(DM) insertion loss with arbitrary input/output impedance is accomplished using a 4-ports S-parameters system for consideration of unbalanced factor. Using this method, when input/output used in specific system is known, CM/DM insertion loss of EMI filter inserted in the system can be calculated. Finally, we applied 4-ports modeling method to 'X/Y capacitor part' and suggested the algorithm for selecting suitable the value of Y-capacitor using mixed mode S-parameters and mixed mode chain S-parameters.

Balanced Mixer Based on Composite Right/Left-Handed Transmission Line Leaky-Wave Antenna (CRLH 전송 선로 리키 웨이브 안테나를 이용한 평형 믹서)

  • Kim, Young
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.19 no.9
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    • pp.985-991
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    • 2008
  • This paper presents a novel balanced mixer receiver front-end design based on a metamaterial structure applicable to differential-/common-mode excitation. This metamaterial structure functions as a leaky-wave antenna and provides in-trinsic common-mode suppression. Low LO leakage and high RF to LO isolation are achieved without additional filters for LO and RF paths. The metamaterial is based on a unit-cell which under a differential-mode excitation behaves like a composite right/left-handed(CRLH) metamaterial. In contrast, the metamaterial unit-cell is below cut-off under a common-mode excitation. Experimental results are used to verify the proposed metamaterial's differential-/common-mode characteristics. The metamaterial is integrated with a balanced mixer design resulting in an operation frequency range of $1.96{\sim}2.40$ GHz with an optimum mixer conversion loss of 21.1 dB at 2,4 GHz.

EMC Design and Evaluation in Conduction Environment (전도성 EMC 설계 및 검증기술)

  • Kim, Tae-Yun;Im, Seong-Bin;Choe, Seok-Won
    • Aerospace Engineering and Technology
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    • v.5 no.2
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    • pp.67-76
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    • 2006
  • This paper describes the analysis method to define the system specification for conducted EMI environment and verification method to evaluate the conducted EMI performance. Conducted EMI environment is characterized by the electrical power subsystem which is mainly issued by the switching circuit noise, common ground impedance coupling. To define and control these EMI problems, EMI assesment through system analysis are preceded at the early design phase and then EMI reduction methods are applied during the unit/system development phase. System EMC should be carefully controlled and designed in the consideration of EMC safety margin and its performance is fully evaluated at the whole development period.

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A 2.4-GHz Low-Power Direct-Conversion Transmitter Based on Current-Mode Operation (전류 모드 동작에 기반한 2.4GHz 저전력 직접 변환 송신기)

  • Choi, Joon-Woo;Lee, Hyung-Su;Choi, Chi-Hoon;Park, Sung-Kyung;Nam, Il-Ku
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.48 no.12
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    • pp.91-96
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    • 2011
  • In this paper, a low-power direct-conversion transmitter based on current-mode operation, which satisfies the IEEE 802.15.4 standard, is proposed and implemented in a $0.13{\mu}m$ CMOS technology. The proposed transmitter consists of DACs, LPFs, variable gain I/Q up-conversion mixer, a divide-by-two circuit with LO buffer, and a drive amplifier. By combining DAC, LPF, and variable gain I/Q up-conversion mixer with a simple current mirror configuration, the transmitter's power consumption is reduced and its linearity is improved. The drive amplifier is a cascode amplifier with gain controls and the 2.4GHz I/Q differential LO signals are generated by a divide-by-two current-mode-logic (CML) circuit with an external 4.8GHz input signal. The implemented transmitter has 30dB of gain control range, 0dBm of maximum transmit output power, 33dBc of local oscillator leakage, and 40dBc of the transmit third harmonic component. The transmitter dissipates 10.2mW from a 1.2V supply and the die area of the transmitter is $1.76mm{\times}1.26mm$.

Three Level Buck Converter Utilizing Multi-bit Flying Capacitor Voltage Control (멀티비트 플라잉 커패시터의 전압제어를 이용한 3-레벨 벅 변환기)

  • So, Jin-Woo;Yoon, Kwang-Sub
    • Journal of IKEEE
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    • v.22 no.4
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    • pp.1006-1011
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    • 2018
  • This paper proposes a three level buck converter utilizing multi-bit flying capacitor voltage control. The conventional three-level buck converter can not control the flying capacitor voltage, so that the operation is unstable or the circuit for controlling the flying capacitor voltage can not be applied to the PWM mode. Also when the load current is increased, an error occurs in the inductor voltage. The proposed structure can control the flying capacitor voltage in PWM mode by using differential difference amplifier and common mode feedback circuit. In addition, this paper proposes a 3bit flying capacitor voltage control circuit to optimize the operation of the three level buck converter depending on the load current, and a triangular wave generation circuit using the schmitt trigger circuit. The proposed 3-level buck converter is designed in $0.18{\mu}m$ CMOS process and has an input voltage range of 2.7V~3.6V and an output voltage range of 0.7V~2.4V. The operating frequency is 2MHz, the load current range is 30mA to 500mA, and the output voltage ripple is measured up to 32.5mV. The measurement results show a maximum power conversion efficiency of 85% at a load current of 130 mA.

Numerical Analysis of Combustion Characteristics during Mode Transfer Period in a Lean Premixed Gas Turbine for Power Generation (발전용 희박예혼합 가스터빈에서 연소모드변환 시기의 연소특성 해석)

  • Chung Jae Hwa;Seo Seok Bin;Kim Jong Jin;Cha Dong Jin;Ahn Dal Hong
    • Proceedings of the KSME Conference
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    • 2002.08a
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    • pp.279-282
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    • 2002
  • Recently, gas turbines for power generation adopt multistage DLN(Dry Low NOx) type combustion, where diffusion combustion is applied at low load and, with increase in load, the combustion mode is changed to lean premixed combustion to reduce NOx emissive concentration. However, during the mode changeover from diffusion to premixed flame, unfavorable phenomena, such as flashback, high amplitude combustion oscillations, or thermal damage of combustor parts could frequently occur. In the present study, to apply for the analysis of such unfavorable phenomena, three-dimensional CFD investigations are carried out to compare the detailed flow characteristics and temperature distribution inside the gas turbine combustor before and after combustion mode changeover. The fuel considered here is pure methane gas. A standard $k-{\varepsilon}$ turbulence model with wall function and a P-N type radiation heat transfer model, have been utilized. To analyze the complex geometric effects of combustor parts on combustion characteristics, fuel nozzles, a swirl vane f3r fuel-air mixing, and cooling air holes on the combustor liner wall, are included in this simulation.

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A Study on the Tele-Controller System of Navigational Aids Using CDMA Communication (CDMA 통신을 이용한 항로표지의 원격관리시스템에 관한 연구)

  • Jeon, Joong-Sung;Oh, Jin-Seok
    • Journal of Advanced Marine Engineering and Technology
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    • v.33 no.8
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    • pp.1254-1260
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    • 2009
  • CDMA tele-Controller system is designed with a low power consumption 8 bit microcontroller, ATmega 2560. ATmega 2560 microcontroller consists of 4 UART (Universal asynchronous receiver/transmitter) ports, 4 kbytes EEPROM, 256 kbytes flash memory, 4 kbytes SRAM. 4 URAT is used for CDMA modem, communication for GPS module, EEPROM is used for saving a configuration for program running, a flash memory of 256 kbytes is used for storing a F/W(Firm Ware), and SRAM is used for stack, storing memory of global variables while program running. We have tested the communication distance between the coast station and sea by the fabricated control board using 800 MHz CDMA modem and GPS module, which is building for the navigational aid management system by remote control. As a results, the receiving signal strength is above -80 dBm, and then the characteristics of the control board implemented more than 10 km in the distance of the communication.

Low power 3rd order single loop 16bit 96kHz Sigma-delta ADC for mobile audio applications. (모바일 오디오용 저 전압 3 차 단일루프 16bit 96kHz 시그마 델타 ADC)

  • Kim, Hyung-Rae;Park, Sang-Hune;Jang, Young-Chan;Jung, Sun-Y;Kim, Ted;Park, Hong-June
    • Proceedings of the IEEK Conference
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    • 2005.11a
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    • pp.777-780
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    • 2005
  • 모바일 오디오 적용을 위한 저전력 ${\Sigma}{\Delta}$ Modulator 에 대한 설계와 layout 을 보였다. 전체 구조는 3 차 단일 피드백 루프이며, 해상도는 16bit 을 갖는다. 샘플링 주파수에 따른 Over-sampling Ratio 는 128(46kHz) 또는 64(96kHz) 가 되도록 하였다. 차동 구조를 사용한 3 차 ${\Sigma}{\Delta}$ modulator 내의 적분기에 사용된 Op-Amp 는 DC-Gain 을 높이기 위해서 Gain-boosting 기법이 적용되었다. ${\Sigma}{\Delta}$ modulator 의 기준 전압은 전류 모드 Band-Gap Reference 회로에서 공급이 되며, PVT(Process, Voltage, Temperature) 변화에 따른 기준 전압의 편차를 보정하기 위하여, binary 3bit 으로 선택하도록 하였다. DAC 에서 사용되는 단위 커패시터의 mismatch 에 의한 성능 감소를 막기 위해, DAC 신호의 경로를 임의적으로 바꿔주는 scrambler 회로를 이용하였다. 4bit Quantizer 내부의 비교기 회로는 고해상도를 갖도록 설계하였고, 16bit thermometer code 에서 4bit binary code 변환시 발생하는 에러를 줄이기 위해 thermometer-to-gray, gray-to-binary 인코딩 방법을 적용하였다. 0.18um CMOS standard logic 공정 내 thick oxide transistor(3.3V supply) 공정을 이용하였다. 입력 전압 범위는 2.2Vp-p,diff. 이며, Typical process, 3.3V supply, 50' C 시뮬레이션 조건에서 2Vpp,diff. 20kHz sine wave 를 입력으로 할 때 SNR 110dB, THD 는 -95dB 이상의 성능을 보였고, 전류 소모는 6.67mA 이다. 또한 전체 layout 크기는 가로 1100um, 세로 840um 이다.

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A 12.5-Gb/s Low Power Receiver with Equalizer Adaptation (이퀄라이저 적응기를 포함한 12.5-Gb/s 저전력 수신단 설계)

  • Kang, Jung-Myung;Jung, Woo-Chul;Kwon, Kee-Won;Chun, Jung-Hoon
    • Journal of the Institute of Electronics and Information Engineers
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    • v.50 no.12
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    • pp.71-79
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    • 2013
  • This paper describes a 12.5 Gb/s low-power receiver design with equalizer adaptation. The receiver adapts to channel and chip process variation by adaptation circuit using sampler and serializer. The adaptation principle is explained. It describes technique receiving ground referenced differential signal of voltage-mode transmitter for low-power. The CTLE(Continuous Time Linear Equalizer) having 17.6 dB peaking gain to remove long tail ISI caused channel with -21 dB attenuation. The voltage margin is 210 mV and the timing margin is 0.75 UI in eye diagram. The receiver consumes 0.87 mW/Gb/s low power in 45 nm CMOS technology.