• 제목/요약/키워드: 직접접합

검색결과 284건 처리시간 0.023초

홈파기를 이용한 새로운 실리콘 직접접합 기술 (A Novel Silicon Direct Bonding Technology using Groove Matrix)

  • 김은동;김남균;김상철;박종문;이승환
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 1995년도 추계학술대회 논문집
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    • pp.81-84
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    • 1995
  • A reliable bonding between two silicon wafers, regularly grooved and non-grooved, was done by the direct boning technology, It is Presented that high structural duality was realized not only at the bended interface but in the bulk, commensurate with the filling of artificial grooves, which would be attributed to the dislocation-gettering capability of groove free-surfaces during annealing. The groove filling would be explained with mass-transport phenomena assisted by the dislocation movement from initial contact boundaries toward groove surfaces. Intrinsic voids can be easily removed by aid of the grooves. The proposed method yielded also an intimate bonding not only between {111} wafers strongly misoriented and slightly inclined to {111} basal plane but even between {111} and {100} orientation wafers.

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CVD 절연막을 이용한 3C-SiC기판의 직접접합에 관한 연구 (A Study on Direct Bonding of 3C-SiC Wafers Using PECVD Oxide)

  • 정연식;류지구;정귀상
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2002년도 하계학술대회 논문집
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    • pp.164-167
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    • 2002
  • SiC direct bonding technology is very attractive for both SiCOI(SiC-on-insulator) electric devices and SiC-MEMS applications because of its application possibility in harsh environments. This paper presents on pre-bonding according to HF pre-treatment conditions in SiC wafer direct bonding using PECVD oxide. The characteristics of bonded sample were measured under different bonding conditions of HF concentration, and applied pressure. The 3C-SiC epitaxial films grown on Si(100) were characterized by AFM and XPS, respectively. The bonding strength was evaluated by tensile strength method. Components existed in the interlayer were analyzed by using FT-IR. The bond strength depends on the HF pre-treatment condition before pre-bonding (Min : 5.3 kgf/$\textrm{cm}^2$∼Max : 15.5 kgf/$\textrm{cm}^2$).

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극한 환경 MEMS용 3C-SiC기판의 직접접합 (Direct Bonding of 3C-SiC Wafer for MEMS in Hash Environments)

  • 정연식;이종춘;정귀상
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2002년도 하계학술대회 논문집 C
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    • pp.2020-2022
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    • 2002
  • SiC direct bonding technology is very attractive for both SiCOI(SiC-on-insulator) electric devices and SiC-MEMS fileds because of its application possibility in harsh environements. This paper presents on pre-bonding according to HF pre-treatment conditions in SiC wafer direct bonding using PECVD oxide. The PECVD oxide was characterized by XPS and AFM, respectively. The characteristics of bonded sample were measured under different bonding conditions of HF concentration and applied pressure, respectively. The bonding strength was evaluated by tensile strength method. Components existed in the interlayer were analyzed by using FT-IR. The bond strength depends on the HF pre-treatment condition before pre-bonding (Min : 5.3 kgf/$cm^2{\sim}$ Max : 15.5 kgf/$cm^2$).

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열처리 방법에 따른 이종절연층 실리콘 기판쌍의 직접접합 (Direct Bonding of Heterogeneous Insulator Silicon Pairs using Various Annealing Method)

  • 송오성;이기영
    • 한국전기전자재료학회논문지
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    • 제16권10호
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    • pp.859-864
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    • 2003
  • We prepared SOI(silicon-on-insulator) wafer pairs of Si II SiO$_2$/Si$_3$N$_4$ II Si using wafer direct bonding with an electric furnace annealing(EFA), a fast linear annealing(FLA), and a rapid thermal annealing(RTA), respectively, by varying the annealing temperatures at a given annealing process. We measured the bonding area and the bonding strength with processes. EFA and FLA showed almost identical bonding area and theoretical bonding strength at the elevated temperature. RTA was not bonded at all due to warpage, We report that FLA process was superior to other annealing processes in aspects of surface temperature, annealing time, and bonding strength.

전기화학적 식각정지에 의한 SOI 박막화에 관한 연구 (A study on SOI structures thinning by electrochemical etch-stop)

  • 강경두;정수태;류지구;정재훈;정귀상
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2000년도 추계학술대회 논문집
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    • pp.583-586
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    • 2000
  • The non-selective method by polishing after grinding was used widely to thinning of SDB SOI structures. This method was very difficult to thickness control of thin film, and it was dependent on equipments. However electrochemical etch-stop, one of the selective methods, was able to accurately thickness control and etch equipment was very simple. Therefore, this paper described with the effect of leakage current and electrodes on electrochemical etch-stop. Consequentially, PP(passivation potential) was changed according to the kinds of contact and contact sizes, but OCP(open current potential) was not change with range of -1.5~-1.3V

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SDB와 전기화학적 식각정지에 의한 매몰 cavity를 갖는 SOI구조의 제작 (Fabrication of SOI structures whit buried cavities by SDB and elelctrochemical etch-stop)

  • 강경두;정수태;류지구;정재훈;김길중;정귀상
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2000년도 추계학술대회 논문집
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    • pp.579-582
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    • 2000
  • This paper described on the fabrication of SOI(Si-on-insulator) structures with buried cavities by SDB technology and eletrochemical etch-stop. The cavity was fabricated the upper handling wafer by Si anisotropic etch technique. SDB process was performed to seal the fabricated cavity under vacuum condition at -760mmHg. In the SDB process, captured air and moisture inside of the cavities were removed by making channels towards outside. After annaling(100$0^{\circ}C$, 60 min.), the SDB SOI structure was thinned by electrochemical etch-stop. Finally, it was fabricated the SDB SOI structure with buried cavities as well as an accurate control and a good flatness.

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전기화학적 식각정지에 의한 SDB SOI기판의 제작 (The Fabrication of a SDB SOI Substrate by Electrochemical Etch-stop)

  • 정귀상;강경두
    • 한국전기전자재료학회논문지
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    • 제13권5호
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    • pp.431-436
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    • 2000
  • This paper describes on the fabrication of a SOI substrate by SDB technology and electrochemical etch-stop. The surface of the thinned SDB SOI substrate is more uniform than that of grinding or polishing by mechanical method and this process was found to be a very accurate method for SOI thickness control. During electrochemical etch-stop leakage current versus voltage curves were measured for analysis of the open current potential(OCP) point the passivation potential(PP) point and anodic passivation potential. The surface roughness and the controlled thickness selectivity of the fabricated a SDB SOI substrate were evaluated by using AFM and SEM respectively.

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특집: 미래주도형 성형공정과 수치 해석기술 - 전자기 성형과 수치 해석 기술

  • 김대용;김지훈
    • 기계와재료
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    • 제23권3호
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    • pp.30-47
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    • 2011
  • 전자기 성형 공정은 강한 전이 자기장을 가공하고자 하는 금속에 직접 작용시켜 금속을 변형시키는 가공 기술로 최근 난성형성 소재의 성형 및 이종 소재의 접합 등에 장점을 가지고 있어 관심이 높아지고 있다. 또한, 전자기 성형 공정을 기존의 스템핑, 하이드로포밍과 같은 성형 공정의 단점을 보완하는 공정으로 이용하여 자동차 부품에 적용하려는 연구가 시도되고 있다. 전기, 자기, 열, 변형을 포함하는 복잡한 물리 현상이 관련되어 있는 전자기 성형 공정을 모사하기 위해서 각 물리 현상들을 연계하여 수치적으로 계산해 내는 기술에 대한 연구가 다각도로 진행 중이다. 본 고에서는 전자기 성형 기술에 대한 개념과 최신 국내외 기술 동향을 소개한 후, 전자기 성형의 수치 해석 기술에 대한 연구 동향을 정리하였다.

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미세수준의 그루브 패턴에서 조골세포 분화 연구 (Osteoblastic Differentiation on Small-Scaled Grooved Patterns)

  • 김진희
    • 한국콘텐츠학회:학술대회논문집
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    • 한국콘텐츠학회 2017년도 춘계 종합학술대회 논문집
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    • pp.489-490
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    • 2017
  • 골유착은 비골조직의 삽입없이 뼈와 금속간의 직접적인 접합으로 치과 임플란트나 정형외과적 기구의 임상적 성공여부를 판가름 짓는 중요한 요소이다. 현재까지 골유착을 향상시킨다 알려진 패턴은 일부 알려져 있지만, 표면패턴이 제한적이라 기대만큼 큰 발전을 이루지 못했다. 본 연구는 특정 그루브 패턴이 조골세포의 분화를 조절할 수 있음을 보여주면, 특정 패턴에서 조골세포의 분화를 강화시킬 수 있다는 계념은 치과의 임플란트나 정형외과 의료기기에 개발에 중요한 기초를 제공할 수 있으리라 사료된다.

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