• Proceedings of the Korean Information Science Society Conference
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• 2004.10a
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• pp.562-564
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• 2004

캐시 선인출 기법은 메모리 참조에 따른 지연시간을 줄이는 효과적인 방법이다. 그러나 너무 적극적인 선인출은 캐시 오염을 유발시켜 선인출에 의한 장점을 상쇄시킨다. 본 연구에서는 캐시의 오염을 줄이기 위해 동적으로 필터 테이블을 참조하여 선인출 명령을 수행할 지의 여부를 결정하는 4가지 필터링 방법들을 비교 평가한다. 비교 연구를 위한 이상적인 필터링 구조를 제안하였으며, 기존 연구에서의 잠김 현상을 개선하기 위한 이진 상태 구조를 제안하였다. 또한, 정교한 필터링을 위한 블록주소 참조 방식을 제안하였다. 일반적으로 많이 사용되는 일반 벤치마크 프로그램과 멀티미디어 벤치마크 프로그램들에 대하여 실험한 결과, 캐시 미스율이 이진 상태 구조는 평균 5.6%, 블록주소 참조 구조는 7.9% 각각 감소하였다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.12A
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• pp.1971-1977
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• 2001

Multipath Rayleigh fading channels for mobile radio transmission can be represented by the linear filter model, and depending on the delay path characteristics, only a selected number of taps may have significance in the receiver structure design. By using tap-selective equalization, reduction in both processing complexity and power consumption can be obtained. In this paper, we present an optimal tap selection method for a given channel model, and demonstrate the performance improvement over an existing method. We show the method performs the CFAR (Constant False Alarm Rate) detection when the noise power information is available, and derive exact expressions of the error probability for the case of noise power estimation. Using the derived formulas and simulation results, it is demonstrated that the error probability quickly approaches to the optimal performance as the number samples used for the noise power estimation increases.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.46 no.2
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• pp.108-113
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• 2009

FIR upsampling circuit generates output data L times faster than input data. For efficient implementation of upsampler, FT filter stages Noble identity theory. In this paper, we propose a method that one of the divided filter stages is removed by making Phase delay to integer number. 192taps 2-times upsampler used in CDtoDAT is designed using proposed method. The designed circuit is synthesized using Hynix 0.18um process. By the simulation results, it is shown that the proposed method leads to up to 48%, 43% and 99.9% and 68% reduction in area, power consumption and maximum phase delay error and maximum ripple error compared with conventional method.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2006.05a
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• pp.43-44
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• 2006

The performance of the direct adaptive time-delay filter depends on the select time-delay. In this paper, the authors introduce a new scheme to adapt the time-delay which is to be used in conjunction with the direct adaptive command shaping for the improved vibration suppression in flexible motion system. In order to formulate the time-delay adaptation scheme, the authors have analyzed the effect of the time-delay value on the performance of the direct adaptive command shaping filter. By modifying the direct adaptation formula based on the analysis result the authors have established a set of equations to adapt the time-delay toward the optimal value. Simulation results show the effectiveness of the proposed time-delay adaptation approach for the improved vibration suppression.

• Proceedings of the Korean Society Of Semiconductor Equipment Technology
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• 2003.05a
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• pp.8-11
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• 2003

본 연구는 AC서보 모터의 벡터 제어를 구현하는데 있어 디지털 제어에 의한 시간 지연 및 Af) 변환기, QEP(Quadrature Encoder Pulse Circuit)등 주변 소자의 시간 지연에 의한 노이즈를 최소화하지 위하여 고성능 저 전압형 DSP인 TMX320F2812를 사용하였다. TMX320F2812는 150MIPS의 빠른 연산 속도와 12비트의 AD 컨버터, QEP회로는 물론 공간 전압 벡터 PWM을 발생시킬 수 있는 기능을 가진 모터 제어용 원친 DSP이다. 이와 같이 주변 회로들을 내장한 고성능 DSP의 사용은 모터 제어부의 하드웨어적인 구성을 간소화 시키고 이로 인한 비용 절감을 얻을 수 있다. 또한 전류 샘플을 위한 필터 부분을 디지털 필터화 하여 전류 샘플링 노이즈를 제거하였고, 옵셋 전압을 이용한 SVPWM을 구현하여 연산 시간을 대폭 단축 하였다. TMX320F2812의 단점인 고정 소수점 연산에 대해서는 각 변수에 대한 스케일링을 통해 유효 자리를 확보하였다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.9 s.351
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• pp.64-68
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• 2006

Novel system-on-package (SOP) - D technology to improve the mechanical and thermal properties of a MCM-D substrate was suggested. Based on this investigation, the two types of band pass filters for the V-band application with unique structure were designed and implemented using 2-metals, 3-BCB layers. The first type using distributed resonator had the insertion loss below 2.6 dB at 55 GHz and group delay was below 0.06 ns. For the second type with edge coupled structure, the insertion loss and group delay were 3 dB and 0.1 ns, respectively. Suggested MCM-D substrate with band pass filter can be used to evaluate mm-Wave system including flip-chip bonded MMIC.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 1999.11b
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• pp.239-242
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• 1999

본 논문에서는 8VSB수신기가 다중경로신호에 따른 성능이 나쁜 것에 대한 원인 분석과 나아가 개선책을 제시하기 위해 다중경로 신호가 디지털 지상파 TV의 수신성능에 미치는 영향에 대해 수신단의 STR(Symbol Timing Recovery)과 등화기를 중심으로 분석한다. 첫째 등화기의 성능 분석을 위해 에코의지연시간이 7.5 $\mu$sec일 때 시불변 환경에서 전산 모의 실험을 하였다. 등화기 수렴후의 에로 레벨에 따른 TOV(Threshold of Visibility) S/N(Signal to Noise)를 구해보면 호주의 실험실 측정과는 달리 0dB에서도 S/N이 26dB 정도이면 등화기는 안정적으로 수렴한다. 둘째 세그먼트 동기 복원을 세그먼트 싱크 필터(Segment Sync:+1, +1. -1, -1)를 사용했을 때 짧은 시간 지연 에코와 긴 시간 지연 에코에 대해 S 커브를 보면 짧은 시간 지연에코에서는 심볼 타이밍이 어긋났으며 긴 시간 지연 에로에서는 문제가 없이 타이밍 동기가 된다. 셋째 짧은 시간 지연 에코신호가 있을 때 세그먼트 동기 복원과 등화기를 연동한 전산 모의 실험을 하여 에코의 영향을 분석하고 FSE(Fractionally Spaced Equalizer) 등화기 사용에 따른 장점을 분석한다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.6
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• pp.51-56
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• 2010

In this paper, a novel Integer-N phase-delay locked loop(P DLL) architecture has been proposed using a voltage controlled delay line(VCDL). The P DLL can have the LF of one small capacitance instead of the conventional second or third-order LF. The size of chip is $255{\mu}m$ $\times$ $935.5{\mu}m$ including the LF. The proposed P DLL has been designed based on a 1.8V $0.18{\mu}m$ CMOS process and proved by HSPICE simulation.

• Journal of the Korean Geosynthetics Society
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• v.6 no.1
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• pp.33-38
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• 2007

PVD (Prefabricated Vertical drain) consists of filter and core. An effective PVD has two basic filtration functions ; first to retain soil particle ; and second, to allow water to pass from the soil into the PVD core without clogging or blinding. Clogging which reduces the permeability of the geotextile filter jacket is caused by fine particles penetrating into the geotextile filter jacket in relatively low permeability soil conditions. As clogging performance increases gradually, excess pore water flow from soil is resisted and finally consolidation delays. Current soil-geotextile filter system criteria are generally based on relationships between a representative pore size of the geotextile and particle size of the soil. In Korea, PVD geotextile filter system criteria have been applied by only testing AOS (Apparent Opening Size) of filters without evaluating the filtration and clogging performance on soil-geotexile filter systems. Therefore, the filtration tests on soil-geotexile filter systems were conducted in order to evaluate the filtration and clogging performance with 3 kinds of geotextile filters. On these tests, we have applied geotextile filter system criteria on PVD in ${\bigcirc}{\bigcirc}$ sites.

• Journal of the Korean Institute of Intelligent Systems
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• v.14 no.5
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• pp.571-576
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• 2004

This paper presents a delay dependent fuzzy $H_{\infty}$ controller design method for delayed fuzzy dynamic systems. Using delay-dependent Lyapunov function, the global exponential stability and $H_{\infty}$ performance problem arc discussed. A sufficient conditions for the existence of fuzzy controller is presented in terms of linear matrix inequalities(LMIs). A simulation example is given to illustrate the design procedures and performances of the proposed methods.