• Proceedings of the KIPE Conference
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• 2014.07a
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• pp.451-452
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• 2014

본 논문에서는 단상 계통연계형 컨버터의 전원 위상각을 추종함에 있어 필수적인 전압 센서의 옵셋 오차에 대한 영향을 분석하고 이를 검출 및 보상하기 위한 알고리즘을 제안하였다. 전원전압 측정에 따른 옵셋 오차는 전원 주파수의 1배 맥동을 야기하여 전원 위상각이 왜곡된다. 왜곡된 전원 위상각에 의한 좌표변환시 동기 좌표계 dq축 전류에 전원 주파수 1배의 맥동을 야기하며 이는 계통측 상전류에 직류성분과 전원 주파수 2배의 고조파 성분을 발생시키게 된다. 따라서, 본 논문에서는 전원측정시 야기되는 옵셋 오차의 영향을 분석하고 이의 검출신호로 전원 위상각 제어기의 적분출력을 선정하였다. 또한 RMS(Root Mean Square) 기법을 이용하여 옵셋 성분을 검출 및 보상하는 알고리즘을 제안하였다. 제안된 알고리즘의 성능은 시뮬레이션과 실험을 통하여 검증하였다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.5
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• pp.1155-1161
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• 2014

This paper proposes a start-up voltage generator for reducing the minimum input supply voltage of DC-DC boost converters to 250mV. The proposed start-up voltage generator boosts 250mV input voltage to over 500mV to charge the capacitor for starting the boost converter. After the boost converter operates initially with the supply voltage charged in the capacitor, it uses its boosted output voltage for the supply voltage. Therefore, after the start-up operation, the proposed DC-DC boost converter works as the same as the conventional one. The proposed start-up voltage generator reduces the threshold voltage of the transistors by adjusting the body voltage at a low input voltage. This causes the higher clock frequency and the larger current to a Dickson charge-pump for boosting the input voltage. The proposed start-up voltage generator was implemented with a $0.18{\mu}m$ CMOS process. Its clock frequency and output voltage were 34.5kHz and 522mV at 250mV input voltage, respectively.

• Journal of Sensor Science and Technology
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• v.9 no.4
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• pp.288-296
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• 2000

Thin-film chromel-alumel multijunction thermal converters with a low output resistance of $64{\sim}85\;{\Omega}$ showed approximately the square law-dependent input-output relation. The voltage responsivities were very low with $0.34{\sim}0.67\;V/W$ in air and $1.15{\sim}1.48\;V/W$ in vacuum, respectively, and the ac-dc voltage transfer error was very large with about +340 ppm in the frequency range of $40\;Hz{\sim}10\;kHz$ in the case of 1 V-input sinewave rms voltage. It can be concluded that the large transfer error of the thermal converter was mainly caused by the low voltage responsivity and the large heat loss due to low output resistance, which implies that the optimization for small ac-dc transfer error is required.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.1
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• pp.149-155
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• 2015

This paper proposes 5-MS/s 10-bit digital-to-analog converter(DAC) with the improved linearity. The proposed DAC consists of a 10-bit R-2R-based DAC, an output buffer using a differential voltage amplifier with rail-to-rail input range, and a band-gap reference circuit for the bias voltage. The linearity of the 10-bit R-2R DAC is improved as the resistor of 2R is implemented by including the turn-on resistance of an inverter for a switch. The output voltage range of the DAC is determined to be $2/3{\times}VDD$ from an rail-to-rail output voltage range of the R-2R DAC using a differential voltage amplifier in the output buffer. The proposed DAC is implemented using a 1-poly 8-metal 130nm CMOS process with 1.2-V supply. The measured dynamic performance of the implemented DAC are the ENOB of 9.4 bit, SNDR of 58 dB, and SFDR of 63 dBc. The measured DNL and INL are less than +/-0.35 LSB. The area and power consumption of DAC are $642.9{\times}366.6{\mu}m^2$ and 2.95 mW, respectively.

• Journal of IKEEE
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• v.22 no.4
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• pp.1006-1011
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• 2018

This paper proposes a three level buck converter utilizing multi-bit flying capacitor voltage control. The conventional three-level buck converter can not control the flying capacitor voltage, so that the operation is unstable or the circuit for controlling the flying capacitor voltage can not be applied to the PWM mode. Also when the load current is increased, an error occurs in the inductor voltage. The proposed structure can control the flying capacitor voltage in PWM mode by using differential difference amplifier and common mode feedback circuit. In addition, this paper proposes a 3bit flying capacitor voltage control circuit to optimize the operation of the three level buck converter depending on the load current, and a triangular wave generation circuit using the schmitt trigger circuit. The proposed 3-level buck converter is designed in $0.18{\mu}m$ CMOS process and has an input voltage range of 2.7V~3.6V and an output voltage range of 0.7V~2.4V. The operating frequency is 2MHz, the load current range is 30mA to 500mA, and the output voltage ripple is measured up to 32.5mV. The measurement results show a maximum power conversion efficiency of 85% at a load current of 130 mA.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.10
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• pp.69-75
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• 2004

This work proposes an 8b 220 MS/s 230 mW 3-stage pipeline CMOS ADC with on-chip filers for temperature- and power- insensitive voltage references. The proposed RC low-pass filters improve switching noise performance and reduce reference settling time at heavy R & C loads without conventional off-chip large bypass capacitors. The prototype ABC fabricated in a 0.25 um CMOS occupies the active die area of 2.25 $\textrm{mm}^2$ and shows the measured DNL and INL of maximum 0.43 LSB and 0.82 LSB, respectively. The ADC maintains the SNDR of 43 dB and 41 dB up to the 110 MHz input at 200 MS/s and 220 MS/s, respectively, while the SNDR at the 500 MHz input is degraded as much as only 3 dB than the SNDR at the 110 MHz input.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.13 no.4
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• pp.96-101
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• 1999

Load model is very important to improve accuracy of stability analysis and load flow study in power systems. A power system bus is composed by various loads, and loads have different power consumption due to voltage/frequency changing. Thus the effect of voltage/frequency changing must he considered to load mxleling. In this research, ANN was used to construct component load moddel for more accurate load mxleling. Typical residential load was selected, and characteristics exrerimented on voltage/frequency changing. Acquired data used to construct the component ANN model, and aggregation method of component load model was presented based on component load model and composition rate. Furthennore, it's transfomlation method to the mathematical load model to he used at the traditional power system analysis soft wares was also presented.sented.

• Proceedings of the KIEE Conference
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• 2011.07a
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• pp.1179-1180
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• 2011

본 논문은 재생에너지의 고전압크기 변환에 적용하기 위해 출력 정류 다이오드 뒤에 LCL 공진회로를 갖는 푸시풀 컨버터를 나타내었다. 푸시풀 컨버터의 공진회로는 두 배의 스위칭 주파로 동작함으로 공진요소의 값이 작아도 되어 소형 경량이다. 제안된 푸시풀 컨버터 토포로지는 낮은 전압에서 높은 전압까지 안정된 전압을 얻을 수 있다. 실험 컨버터는 입력전압 24[V], 전류 80-A, 출력전압 320[V] 출력 1.5[kW]이고 동작 주파수 20 [kHz]에서 양호하게 동작하였고 시뮬레이션과 실험 결과가 잘 일치함을 볼 수 있다.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.26 no.6
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• pp.533-539
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• 2015

In this paper, we designed a reconfigurable mixer for microwave broadband receiver. The proposed mixer using a anti-parallel diode is operated as a fundamental mixer or sub-harmonic mixer with respect to a control voltage. A fundamental mixer with a control voltage show a conversion loss of -10 dB, 1 dB compression point of 2.0 dBm at X-band/ Ku-band. On the other hand, it is performed as a sub-harmonic mixer with a conversion loss of -17 dB, 1 dB compression point of 2.0 dBm at Ka-band.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.6
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• pp.35-40
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• 2012

This paper has proposed a 3~5 GHz IR-UWB low power transmitter for range detection application. Proposed transmitter which has been implemented in a $0.13{\mu}m$ CMOS technology is all digital circuit that consist of simple digital logic. this feature insure low complexity and low power consumption. In addition, center frequency can be changed by adopting voltage controlled delay cell for avoiding existing another radio frequency in UWB low band. Proposed circuit consume only 10pJ/b from 1.2 V supply voltage. The simulation results show 3.3~4.3 GHz center frequency controllability, -51 dBm/MHz maximum output power and is satisfied with FCC regulation.