• Journal of the Korean Institute of Telematics and Electronics S
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• v.36S no.8
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• pp.8-16
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• 1999

In this paper, the performance of a hybrid DS/SFH-SS(direct-sequence/slow-frequency-hopped spread-spectrum) system with coherent BPSK modulation over Nakagami fading channel in the presence of multiple tone jamming is analyzed. Because the Nakagami m-distribution can describe not only Rayleigh fading but also more general fluctuations involving a specular component by adjusting the value of the fading index m. It is known that for m=1 corresponds to Rayleigh fading, for $1/2{\le}m{\le}1$ corresponds to the worst case fading condition, for m>1 corresponds to Rician fading, and for $m{\to}{\infty}$ corresponds to the nonfading condition. The bit error probability is derived over Nakagami model and numerical evaluations are presented for some combinations of system parameters. The results show that as m increases, the bit error probability is better. Also, at a low JSR(jamming-to-signal power ratio), a pure DS-SS system can achieve lower bit error probability than a hybrid DS/SFH-SS system. But at a high JSR, a hybrid DS/SFH-SS system is shown to be superior to a pure DS-SS system. Therefore, it is demonstrated that without increasing the total system bandwidth, the performance of a hybrid DS/SFH-SS is superior to that of a pure DS-SS system in the presence of multiple tone jamming.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.35S no.8
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• pp.1-11
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• 1998

One of the desired features for the realizations of high quality Information and Telecommunication services in future is "the Sensation of Reality". This will be achieved only with the visual communication based on the 3- dimensional (3-D) moving images. The main difficulties in realizing 3-D moving image communication are that there is no developed data transmission technology for the hugh amount of data involved in 3-D images and no established technologies for 3-D image recording and displaying in real time. The currently known stereoscopic imaging technologies can only present depth, no moving parallax, so they are not effective in creating the sensation of the reality without taking eye glasses. The more effective 3-D imaging technologies for achieving the sensation of reality are those based on the multiview 3-D images which provides the object image changes as the eyes move to different directions. In this paper, a multiview 3-D imaging system composed of 8 CCD cameras in a case, a RGB(Red, Green, Blue) beam projector, and a holographic screen is introduced. In this system, the 8 view images are recorded by the 8 CCD cameras and the images are transmitted to the beam projector in sequence by a signal converter. This signal converter converts each camera signal into 3 different color signals, i.e., RGB signals, combines each color signal from the 8 cameras into a serial signal train by multiplexing and drives the corresponding color channel of the beam projector to 480Hz frame rate. The beam projector projects images to the holographic screen through a LCD shutter. The LCD shutter consists of 8 LCD strips. The image of each LCD strip, created by the holographic screen, forms as sub-viewing zone. Since the ON period and sequence of the LCD strips are synchronized with those of the camera image sampling adn the beam projector image projection, the multiview 3-D moving images are viewed at the viewing zone.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.12
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• pp.99-108
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• 2015

The embedded microcontroller which is operated by the logic gates synchronized on the clock pulse, is gradually used as main controller of mission-critical systems. Severe electrical situations such as high voltage/frequency surge may cause malfunctioning of the clock source. The tolerant system operation is required against the various external electric noise and means the robust design technique is becoming more important issue in system clock failure problems. In this paper, we propose on-chip backup clock change architecture for the automatic clock failure detection. For the this, we adopt the edge detector, noise canceller logic and glitch-free clock changer circuit. The implemented edge detector unit detects the abnormal low-frequency of the clock source and the delay chain circuit of the clock pulse by the noise canceller can cancel out the glitch clock. The externally invalid clock source by detecting the emergency status will be switched to back-up clock source by glitch-free clock changer circuit. The proposed circuits are evaluated by Verilog simulation and the fabricated IC is validated by using test equipment electrical field radiation noise

• Journal of Advanced Navigation Technology
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• v.22 no.5
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• pp.449-455
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• 2018

For the size reduction, we propose a microstrip-fed monopole antenna with half X-slot in the radiation patch and cover WLAN dual band 2.4 GHz band (2.4 ~ 2.484 GHz) and 5 GHz band (5.15 ~ 5.825 GHz). The frequency characteristics such as impedance bandwidth and resonant frequencies were satisfied by optimizing the numerical values of various parameters, while the reflection loss in 5 GHz was improved by using defected ground structure (DGS). The proposed antenna is designed and fabricated on a FR-4 substrate with dielectric constant 4.3, thickness of 1.6 mm, and size of $24{\times}41mm^2$. The measured impedance bandwidths (${\mid}S_{11}{\mid}{\leq}-10dB$) of fabricated antenna are 450 MHz (2.27 ~ 2.72 GHz) in 2.4 GHz band and 1340 MHz (4.79 ~ 6.13 GHz) in 5 GHz band which sufficiently satisfied with the IEEE 802. 11n standard in dual band. In particular, radiation patterns which are stable as well as relatively omni-direction could be obtained, and the gain of antennas in each band was 1.31 and 1.98 dBi respectively.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.8C
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• pp.742-749
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• 2009

In this paper, we propose mitigation techniques using time-domain shortening filter (TSF) and frequency-domain shortening filter (FSF) to overcome inter-block interference (IBn and inter-carrier interference (ICn due to the time difference of arrival (TDoA) and carrier frequency offset (CFO) between downlink and uplink signals from access point (AP) and subscriber station (SS) in synchronous digital duplexing (SDD)/orthogonal frequency division multiple access (OFDMA) systems for indoor wireless communication. The proposed TSF and FSF maximize SIR for shortening in time (SIRST) and SINR for shortening in frequency (SINRSF), respectively, by using channel impulse responses and timing information among stations, obtained from mutual ranging procedure. It is verified by computer simulation that the proposed TSF and FSF reduce effectively the effects of IBI and ICI in the SDD/OFDMA systems.

• Journal of the Computational Structural Engineering Institute of Korea
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• v.29 no.1
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• pp.9-18
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• 2016

The slender structures such as high rise building or marine riser are highly susceptible to dynamic force exerted by fluid-structure interactions among which vortex-induced vibration(VIV) is the main cause of dynamic unstability of the structural system. If VIV occurs in natural frequency regime of the structure, fatigue failure likely happens by so-called lock-in phenomenon. This study presents the numerical analysis of dynamic behavior of both structure and fluid in the lock-in regimes and investigates the subjacent phenomena to hold the resonance frequency in spite of the change of flow condition. Unsteady and laminar flow was considered for a two-dimensional circular cylinder which was assumed to move freely in 1 degree of freedom in the direction orthogonal to the uniform inflow. Fluid-structure interaction was implemented by solving both unsteady flow and dynamic motion of the structure sequentially in each time step where the fluid domain was remeshed considering the movement of the body. The results show reasonable agreements with previous studies and reveal characteristic features of the lock-in phenomena. Not only the lift force but also drag force are drastically increasing during the lock-in regime, the vertical displacement of the cylinder reaches up to 20% of the diameter of the cylinder. The correlation analysis between lift and vertical displacement clearly show the dramatic change of the phase difference from in-phase to out-of-phase when the cylinder experiences lock-in. From the results, it can be postulated that the change of phase difference and flow condition is responsible for the resonating behavior of the structure during lock-in.

• Journal of Sensor Science and Technology
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• v.5 no.5
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• pp.21-29
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• 1996

A piezoresistive silicon acceleration sensor with 8 beams, utilized by an unique silicon micromachining technique using porous silicon etching method which was fabricated on the selectively diffused (111)-oriented $n/n^{+}/n$ silicon subtrates. The width, length, and thickness of the beam was $100\;{\mu}m$, $500\;{\mu}m$, and $7\;{\mu}m$, respectively, and the diameter of the mass paddle (the region suspended by the eight beams) was 1.4 mm. The seismic mass on the mass paddle was formed about 2 mg so as to measure accelerations of the range of 50g for automotive applications. For the formation of the mass, the solder mass was loaded on the mass paddle by dispensing Pb/Sn/Ag solder paste. After the solder paste is deposited, Heat treatment was carried out on the 3-zone reflow equipment. The decay time of the output signal to impulse excitation of the fabricated sensor was observed for approximately 30 ms. The sensitivity measured through summing circuit was 2.9 mV/g and the nonlinearity of the sensor was less than 2% of the full scale output. The output deviation of each bridge was ${\pm}4%$. The cross-axis sensitivity was within 4% and the resonant frequency was found to be 2.15 KHz from the FEM simulation results.

• The KIPS Transactions:PartA
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• v.10A no.3
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• pp.247-254
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• 2003

This paper describes a Delay Locked Loop (DLL) with low supply voltage and wide lock range for Synchronous DRAM which employs Double Data Rate (DDR) technique for faster data transmission. To obtain high resolution and fast lock-on time, a new type of phase detector is designed. The new counter and lock indicator structure are suggested based on the Dual-clock dual-data Flip Flop (DCDD FF). The DCDD FF reduces the size of counter and lock indicator by about 70%. The delay line is composed of coarse and fine units. By the use of fast phase detector, the coarse delay line can detect minute phase difference of 0.2 nsec and below. Aided further by the new type of 3-step vernier fine delay line, this DLL circuit achieves unprecedented timing resolution of 25psec. This DLL spans wide locking range from 500MHz to 500MHz and generates high-speed clocks with fast lock-on time of less than 5 clocks. When designed using 0.25 um CMOS technology with 1.8V supply voltage, the circuit consumes 32mA at 500MHz locked condition. This circuit can be also used for other applications as well, such as synchronization of high frequency communication systems.