• Journal of KIISE:Computer Systems and Theory
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• v.26 no.3
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• pp.380-388
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• 1999

본 논문에서는 완전삼트리를 재귀원형군에 임베딩하는 문제를 고려한다. 재귀원형군 G(N,d)는 N개의 노드와 N보다 작은 d의 거듭제곱에 의한 점프에지를 가지는 원형군그래프이다. 임베딩 문제를 해결하고자 본 논문에서는 노드수가 3k인 삼항트리 Tk새롭게 도입한다. 먼저 N개 이하의 정점을 가지는 삼항트리가 G(N, 2)와 G(N,3)의 부그래프임을 보인다. 또한 완전 삼진트리가 삼항트리에 연장률 2, 확장률2, 밀집률 2로 임베딩됨을 보인다. 이러한 결과들을 결합하면서 N개 이하의 정점을 가지는 완전삼진 트리가 재귀원형군G(2N, 2)과 G(2N, 3)에 연장률 2, 밀집률 2로 임베딩 가능하게 한다. 임베딩 과정에서 이용된 삼항트리는 2 -포트 방송모델에서 최소방송트리임을 보이고, 이를 이용하여 재귀원형군 G(2m, 2)가 2-포트 방송모델에서 최소방송시간을 가짐을 보인다.

• East Asian mathematical journal
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• v.26 no.2
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• pp.267-280
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• 2010

In this paper we study construction methods of $n^{th}$ line in triangle. Russian Mathematician Zetel suggested some construction methods of $n^{th}$ line in triangle 80 years ago. We find Zetel's papers, in detail explain the Zetel's construction methods, and suggest two elementary construction methods. Our results are received in the process of Research and Education program in science high school.

• Journal of Korean Society of Coastal and Ocean Engineers
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• v.10 no.4
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• pp.197-203
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• 1998

An approach of decomposing the reflecting components is proposed by using the mild-slope equation of hyperbolic type which has the similar form to the shallow water equations. The approach is verified on Booij's problem and sinusoidally varying ripples. Inclusion of higher-order bottom effect given by chamberlain and Porter(1995) yields even more satisfactory results than the Berkhoff's mild-slope equation when compared with finite element solution or experiments.

• Journal of the Korean Institute of Telematics and Electronics
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• v.22 no.3
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• pp.31-42
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• 1985

Thig paper used two feedback sensors, that is, potentiometer and tachometer in order to control DC motor. Also, the state feedback and kalman regular type in the linear system or the state feedback and on-off relay type in the non-linear system are used as control meth-ods for optimal control values. This compared and analyzed the control estimate of tracking angles by the estimate of three branches of methods of position and speed measured, position and speed by PD and position, speed and covariance by an observer.

• Journal of the Korean Chemical Society
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• v.49 no.6
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• pp.531-536
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• 2005

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.12
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• pp.12-20
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• 1998

The non-uniform leaky wave structure of the slits in a parallel-plate waveguide is analyzed from the viewpoints of transmitting(receiving) leaky wave antenna and grating coupler. Period and slit width are simultaneously varied along the leaky wave structure to construct the leaky wave structure with a specific distribution of complex propagation constant. Some results for the equivalent magnetic current distributions over the slits and the radiation characteristics of the leaky wave structure with various source(equivalent magnetic current) distributions such as Gaussian, uniform, cosine, cosine-squared, and Taylor distributions are given and compared with each other.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.47 no.1
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• pp.42-46
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• 2010

Encapsulation for information security is often carried out in Galois field in the form of arithmetic operations. This paper proposes how to efficiently perform exponentiation of arithmetic information on Galois field. Especially, by improving an existing bit-parallel exponentiator to exclude elements with heavy gate counts and to take advantage of system constants, this paper proposes how to implement a VLSI architecture with high performance even for large m.

• Journal of KIISE:Computer Systems and Theory
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• v.33 no.1_2
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• pp.62-68
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• 2006

The important arithmetic operations over finite fields include multiplication and exponentiation. An exponentiation operation can be implemented using a series of squaring and multiplication operations over GF($2^m$) using the binary method. Hence, it is important to develop a fast algorithm and efficient hardware for multiplication. This paper presents an efficient bit-serial systolic array for MSB-first multiplication in GF($2^m$) based on the polynomial representation. As compared to the related multipliers, the proposed systolic multiplier gains advantages in terms of input-pin and area-time complexity. Furthermore, it has regularity, modularity, and unidirectional data flow, and thus is well suited to VLSI implementation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.1
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• pp.37-42
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• 2008

In this paper, we propose a partial product addition method using variable groups in the design of operators such as multipliers and digital filters. By this method, full adders can be replaced with simple logic circuits. To show the efficiency of the proposed method, we applied the method to the design of squarers and precomputer blocks of FIR filters. In case of 7 bit and 8 bit squarers, it is shown that by the proposed method, area, power and delay time can be reduced up to {22.1%, 20.1%, 14%} and {24.7%, 24.4%, 6.7%}, respectively, compared with the conventional method. The proposed FIR precomputer circuit leads to up to {63.6%, 34.4%, 9.8%} reduction in area, power consumption and propagation delay compared with previous method.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.6
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• pp.26-33
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• 2002

In this paper, a new four-quadrant MOS analog multiplier Is proposed using the quarter-square technique, which is based on the quadratic characteristics of MOS transistor operating in the saturation region and the difference operation of a source-coupled differential circuits. The proposed circuit has been fabricated in a p-well CMOS process. The multiplier achieves a total harmonic distortion of less than 1 percent for the both input ranges of 50 percent of power supply, a -3㏈ bandwidth of 30㎒ a dynamic range of 81㏈ and a power consumption of 40㎽. The active chip area is 0.54㎟. The supposed multiplier circuit is simple and adjust high frequency application because one input signal transfer output by one transistor.