• Journal of the Institute of Electronics Engineers of Korea SC
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• v.41 no.6
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• pp.27-35
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• 2004

Finite or Galois fields have been used in numerous applications such as error correcting codes, digital signal processing and cryptography. These applications often require exponetiation on GF(2$^{m}$ ) which is a very computationally intensive operation. Most of the existing methods implemented the exponetiation by iterative methods using repeated multiplications, which leads to much computational load, or needed much hardware cost because of their structural complexity in implementing. In this paper, we present an effective VLSI architecture for exponentiation on GF(2$^{m}$ ). This circuit computes the exponentiation by multiplying product terms, each of which corresponds to an exponent bit. Until now use of this type algorithm has been confined to a primitive element but we generalize it to any elements in GF(2$^{m}$ ).

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.3
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• pp.42-47
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• 2011

The partial product matrix (PPM) of a parallel squarer is symmetric. To reduce the depth of PPM, it can be folded, shifted and rearranged. In this paper, we present an area-efficient squarer design method using new partial product rearrangement. Also, a fixed-width squarer design method of the proposed squarer is presented. By simulations, it is shown that the proposed squarers lead to up to 17% reduction in area, 10% reduction in propagation delay and 10% reduction in power consumption compared with previous squarers. By using the proposed fixed-width squarers, the area, propagation delay and power consumption can be further reduced up to 30%, 16% and 28%, respectively.

• Journal of Korea Society of Industrial Information Systems
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• v.7 no.5
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• pp.167-174
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• 2002

This paper analyzes the characteristics of three multipliers and squarers in finite fields GF(2/sup m/) from the point of view of processing time and area complexity. First, we analyze structures of three multipliers and squarers: 1) Systolic array structure, 2), LFSR structure, and 3) CA structure. To make performance analysis, each multiplier and squarer was modeled in VHDL and was synthesized for FPGA implementation. The simulation results show that CA structure is the best from the point view of processing time, and LFSR structure is the best from the point of view of area complexity.

• Journal of KIISE:Computer Systems and Theory
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• v.28 no.6
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• pp.289-300
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• 2001

본 논문에서는 유한 필드 GF(2$_{m}$ ) 상에서 모듈러 곱셈 A($\chi$)B($\chi$) mod P($\chi$)을 수행하는 새로운 선형 문제-크기(full-size) 시스톨릭 어레이 구조인 LSB-first 곱셈기를 제안한다. 피연산자 B($\chi$)의 LSB(least significant bit)를 먼저 사용하는 LSB-first 모듈러 곱셈 알고리즘으로부터 새로운 비트별 순환 방정식을 구한다. 데이터의 흐름이 규칙적인 순환 방정식을 공간-시간 변환으로 새로운 시스톨릭 곱셈기를 설계하고 분석한다. 기존의 곱셈기와 비교할 때 제안한 곱셈기의 면적-시간 성능이 각각 10%와 18% 향상됨을 보여준다. 또한 같은 설계방법으로 곱셈과 제곱연산을 동시에 수행하는 새로운 시스톨릭 곱셈/제곱기를 제안한다. 유한 필드상의 지수연산을 위해서 제안한 시스톨릭 곱셈/제곱기를 사용할 때 곱셈기만을 사용 할 때보다 면적-시간 성능이 약 26% 향상됨을 보여준다.

• Journal of KIISE:Software and Applications
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• v.30 no.7_8
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• pp.744-751
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• 2003

A hybrid least square Support Vector Machine combined with First Principle(FP) knowledge is proposed. We compare hybrid least square Support Vector Machine(HLS-SVM) with early proposed models such as Hybrid Neural Network(HNN) and HNN with Extended Kalman Filter(HNN-EKF). In the training and validation stage HLS-SVM shows similar performance with HNN-EKF but better than HNN, whereas, in the testing stage, it shows three times better than HNN-EKF, hundred times better than HNN model.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.37 no.6
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• pp.70-75
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• 2000

This paper examines the performance of adaptive filtering algorithms in relation to the asymptotic relative efficiency (ARE) of estimators. The adaptive filtering algorithms are Hybrid II and modified zero forcing (MZF) algorithms. The Hybrid II and MZF algorithms are simplified forms of the LMS algorithm, which use the polarity of the input signal, and polarities of the error and input signals, respectively. The ARE of estimators for each algorithm is analyzed under the condition of the same convergence speed. Computer simulations for adaptive equalization are performed to check the validity of the theory. The explicit expressions for the ARE values of the Hybrid II and MZF algorithms are derived, and its results have similar values to the results of computer simulation. It also revealed that the ARE values depend on the correlation coefficients between input signal and error signal.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.49 no.5
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• pp.15-20
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• 2012

In this paper, we show new method to find the error locations of received Reed-Solomon code word. New design is much faster and has much simpler logic circuit than the former design method. This optimization was possible by very simplified square/$X^4$ calculating circuit, parallel processing and not using the very complex Divider. The Reed Solomon decoder using this new Chien Machine can be applicated for data protection of almost all digital communication and consumer electronic devices.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.12
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• pp.150-158
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• 2013

In this paper we present approximated constrained least squares filter for real-time directionally adaptive image restoration. The proposed method makes a hardware implementation easier for real-time image restoration because of reducing the filter size. Furthermore, for directional adaptive image restoration, this paper estimates the local orientation by analyzing the covariance matrix and applies to approximated constrained least squares filter. Experimental results show that the proposed method is sharper and less artifacts than existing methods.

• Journal of KIISE:Computer Systems and Theory
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• v.31 no.1_2
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• pp.1-9
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• 2004

The important arithmetic operations over finite fields include exponentiation, division, and inversion. An exponentiation operation can be implemented using a series of squaring and multiplication operations using a binary method, while division and inversion can be performed by the iterative application of an AB$^2$ operation. Hence, it is important to develop a fast algorithm and efficient hardware for this operations. In this paper presents new bit-serial architectures for the simultaneous computation of multiplication and squaring operations, and the computation of an $AB^2$ operation over $GF(2^m)$ generated by an irreducible AOP of degree m. The proposed architectures offer a significant improvement in reducing the hardware complexity compared with previous architectures, and can also be used as a kernel circuit for exponentiation, division, and inversion architectures. Furthermore, since the Proposed architectures include regularity and modularity, they can be easily designed on VLSI hardware and used in IC cards.

• Journal of KIISE
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• v.45 no.1
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• pp.69-75
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• 2018

In the streaming data where data samples arrive sequentially in time, it is difficult to apply the dimension reduction method based on batch learning. Therefore an incremental dimension reduction method for the application to streaming data has been studied. In this paper, we propose an incremental linear discriminant analysis method using the least squared error solution. Instead of computing scatter matrices directly, the proposed method incrementally updates the projective direction for dimension reduction by using the information of a new incoming sample. The experimental results demonstrate that the proposed method is more efficient compared with previously proposed incremental dimension reduction methods.