Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
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Area-Efficient Squarer and Fixed-Width Squarer Design

저면적 제곱기 및 고정길이 제곱기의 설계

  • Received : 2011.02.28
  • Accepted : 2011.03.11
  • Published : 2011.03.25
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Abstract

The partial product matrix (PPM) of a parallel squarer is symmetric. To reduce the depth of PPM, it can be folded, shifted and rearranged. In this paper, we present an area-efficient squarer design method using new partial product rearrangement. Also, a fixed-width squarer design method of the proposed squarer is presented. By simulations, it is shown that the proposed squarers lead to up to 17% reduction in area, 10% reduction in propagation delay and 10% reduction in power consumption compared with previous squarers. By using the proposed fixed-width squarers, the area, propagation delay and power consumption can be further reduced up to 30%, 16% and 28%, respectively.

제곱기의 부분곱 행렬은 대칭이므로 부분곱을 폴딩(folding), 쉬프트, 재배열하여 부분곱 행렬의 높이를 줄일 수 있다. 본 논문에서는 기존 제곱기와 비교하여 효율적인 제곱기의 설계 방법을 제안한다. 또한, 제안한 제곱기에 대해 고정길이 제곱기의 설계 방법을 제안한다. 시뮬레이션을 통해 제안한 제곱기는 기존 제곱기와 비교하여 면적은 약 17%, 지연시간(propagated delay time)은 약 10%, 전력소모는 약 10%까지 감소시킬 수 있음을 보인다. 제안한 고정길이 제곱기는 기존 고정길이 제곱기와 비교하여 절대오차와 평균오차의 성능비교에서 우수하면서, 일반 제곱기(full-width)와 비교하여 면적, 지연시간, 전력소모를 각각 30%, 16%, 28%까지 감소시킬 수 있음을 보인다.

Keywords

References

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