• Title/Summary/Keyword: 정수나눗셈

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A Design of Interger division instruction of Low Power ARM7 TDMI Microprocessor (저전력 ARM7 TDMI의 정수 나눗셈 명령어 설계)

  • 오민석;김재우;김영훈;남기훈;이광엽
    • Journal of the Institute of Electronics Engineers of Korea CI
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    • v.41 no.4
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    • pp.31-39
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    • 2004
  • The ARM7 TDMI microprocessor employ a software routine iteration method in order to handle integer division operation, but this method has long execution time and many execution instruction. In this paper, we proposed ARM7 TDMI microprocessor with integer division instruction. To make this, we additionally defined UDIV instruction for unsigned integer division operation and SDIV instruction for signed integer division operation, and proposed ARM7 TDMI microprocessor data Path to apply division algorithm. Applied division algorithm is nonrestoring division algorithm and additive hardware is reduced using existent ARM data path. To verify the proposed method, we designed proposed method on RTL level using HDL, and conducted logic simulation. we estimated the number of execution cycles and the number of execution instructions as compared proposed method with a software routine iteration method, and compared with other published integer divider from the number of execution cycles and hardware size.

Design of an ARM7 Core with a Singed Integer Division Instruction (Signed Integer Division 명령어를 추가한 ARM7 Core 설계)

  • 오민석;조태헌;남기훈;이광엽
    • Proceedings of the IEEK Conference
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    • 2003.07d
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    • pp.1391-1394
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    • 2003
  • 본 논문은 ARM7 TDMI 마이크로프로세서의 연산기능 중 구현되지 알은 나눗셈 연산 기능을 추가로 구현하였다. 이를 위해 ARM ISA(Instruction Set Architecture)에 부호를 고려한 나눗셈 명령어인 'SDIV' 명령어를 추가로 정의하였으며, 나눗셈 알고리즘 Signed Nonrestoring Division을 수행할 수 있도록 ARM7 TDMI 마이크로프로세서의 Data Path를 재 설계하였다. 제안된 방법의 타당성을 검증하기 위하여 현재 ARM7 TDMI 마이크로프로세서의 정수 나눗셈 연산처리 방법과 제안된 구조에서의 정수 나눗셈 연산 처리 방법을 비교하였으며, 그 겉과 수행 cycle의 수가 40%로 감소되는 것을 확인하였다

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A Study on Extension of Division Algorithm and Euclid Algorithm (나눗셈 알고리즘과 유클리드 알고리즘의 확장에 관한 연구)

  • Kim, Jin Hwan;Park, Kyosik
    • Journal of Educational Research in Mathematics
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    • v.23 no.1
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    • pp.17-35
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    • 2013
  • The purpose of this study was to analyze the extendibility of division algorithm and Euclid algorithm for integers to algorithms for rational numbers based on word problems of fraction division. This study serviced to upgrade professional development of elementary and secondary mathematics teachers. In this paper, fractions were used as expressions of rational numbers, and they also represent rational numbers. According to discrete context and continuous context, and measurement division and partition division etc, divisibility was classified into two types; one is an abstract algebraic point of view and the other is a generalizing view which preserves division algorithms for integers. In the second view, we raised some contextual problems that can be used in school mathematics and then we discussed division algorithm, the greatest common divisor and the least common multiple, and Euclid algorithm for fractions.

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Double Precision Integer Divider Using Multiplier (곱셈기를 사용한 배정도 정수 나눗셈기)

  • Song, Hong-Bok;Cho, Gyeong-Yeon
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.14 no.3
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    • pp.637-647
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    • 2010
  • This paper suggested an algorithm that uses a multiplier, 'w bit $\times$ w bit = 2w bit', to process $\frac{N}{D}$ integer division of 2w bit integer N and w bit integer D. An algorithm suggested of the research, when the divisor D is '$D=0.d{\times}2^L$, 0.5 < 0.d < 1.0', approximate value of $\frac{1}{D}$, '$1.g{\times}2^{-L}$', which satisfies '$0.d{\times}1.g=1+e$, e < $2^{-w}$', is defined as over reciprocal number and the dividend N is segmented in small word more than 'w-3' bit, and partial quotient is calculated by multiplying over reciprocal number in each segmented word, and quotient of double precision integer division is evaluated with sum of partial quotient. The algorithm suggested in this paper doesn't require additional correction, because it can calculate correct reciprocal number. In addition, this algorithm uses only multiplier, so additional hardware for division is not required to implement microprocessor. Also, it shows faster speed than the conventional SRT algorithm. In conclusion, results from this study could be used widely for implementation SOC(System on Chip) and etc. which has been restricted to microprocessor and size of the hardware.

The Integer Number Divider Using Improved Reciprocal Algorithm (개선된 역수 알고리즘을 사용한 정수 나눗셈기)

  • Song, Hong-Bok;Park, Chang-Soo;Cho, Gyeong-Yeon
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.12 no.7
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    • pp.1218-1226
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    • 2008
  • With the development of semiconductor integrated technology and with the increasing use of multimedia functions in computer, more functions have been implemented as hardware. Nowadays, most microprocessors beyond 32 bits generally implement an integer multiplier as hardware. However, as for a divider, only specific microprocessor implements traditional SRT algorithm as hardware due to complexity of implementation and slow speed. This paper suggested an algorithm that uses a multiplier, 'w bit $\times$ w bit = 2w bit', to process $\frac{N}{D}$ integer division. That is, the reciprocal number D is first calculated, and then multiply dividend N to process integer division. In this paper, when the divisor D is '$D=0.d{\times}2^L$, 0.5 < 0.d < 1.0', approximate value of ' $\frac{1}{D}$', '$1.g{\times}2^{-L}$', which satisfies ' $0.d{\times}1.g=1+e$, $e<2^{-w}$', is defined as over reciprocal number and then an algorithm for over reciprocal number is suggested. This algorithm multiplies over reciprocal number '$01.g{\times}2^{-L}$' by dividend N to process $\frac{N}{D}$ integer division. The algorithm suggested in this paper doesn't require additional revision, because it can calculate correct reciprocal number. In addition, this algorithm uses only multiplier, so additional hardware for division is not required to implement microprocessor. Also, it shows faster speed than the conventional SRT algorithm and performs operation by word unit, accordingly it is more suitable to make compiler than the existing division algorithm. In conclusion, results from this study could be used widely for implementation SOC(System on Chip) and etc. which has been restricted to microprocessor and size of the hardware.

An Efficient Integer Division Algorithm for High Speed FPGA (고속 FPGA 구현에 적합한 효율적인 정수 나눗셈 알고리즘)

  • Hong, Seung-Mo;Kim, Chong-Hoon
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.44 no.2
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    • pp.62-68
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    • 2007
  • This paper proposes an efficient integer division algorithm for high speed FPGAs' which support built-in RAMs' and multipliers. The integer division algorithm is iterative with RAM-based LUT and multipliers, which minimizes the usage of logic fabric and connection resources. Compared with some popular division algorithms such as division by subtraction or division by multiply-subtraction, the number of iteration is much smaller, so that very low latency can be achieved with pipelined implementations. We have implemented our algorithm in the Xilinx virtex-4 FPGA with VHDL coding and have achieved 300MSPS data rate in 17bit integer division. The algorithm used less than 1/6 of logic slices, 1/4 of the built-in multiply-accumulation units, and 1/3 of the latencies compared with other popular algorithms.

A High Performance Modular Multiplier for ECC (타원곡선 암호를 위한 고성능 모듈러 곱셈기)

  • Choe, Jun-Yeong;Shin, Kyung-Wook
    • Journal of IKEEE
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    • v.24 no.4
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    • pp.961-968
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    • 2020
  • This paper describes a design of high performance modular multiplier that is essentially used for elliptic curve cryptography. Our modular multiplier supports modular multiplications for five field sizes over GF(p), including 192, 224, 256, 384 and 521 bits as defined in NIST FIPS 186-2, and it calculates modular multiplication in two steps with integer multiplication and reduction. The Karatsuba-Ofman multiplication algorithm was used for fast integer multiplication, and the Lazy reduction algorithm was adopted for reduction operation. In addition, the Nikhilam division algorithm was used for the division operation included in the Lazy reduction. The division operation is performed only once for a given modulo value, and it was designed to skip division operation when continuous modular multiplications with the same modulo value are calculated. It was estimated that our modular multiplier can perform 6.4 million modular multiplications per second when operating at a clock frequency of 32 MHz. It occupied 456,400 gate equivalents (GEs), and the estimated clock frequency was 67 MHz when synthesized with a 180-nm CMOS cell library.

High-speed Integer Fuzzy Operations Without Multiplications and Divisions (곱셈, 나눗셈이 필요 없는 고속 정수 퍼지 연산)

  • Kim Jin-Il;Lee Sang-Gu
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.10 no.9
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    • pp.1727-1736
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    • 2006
  • In a fuzzy control system to vocess fuzzy data in high-speed for intelligent systems, one of the important problems is the improvement of the execution speed in the fuzzy inference and defuzzification stages. Especially, it is more important to have high-speed operations in the consequent Pan and defuzzification stage. Therefore, in this paper, to improve the speedup of the fuzzy controllers for intelligent systems, we propose novel integer fuzzy operation method without mulitplications and divisions by only integer addition to convert real values in the fuzzy membership functions in the consequent part to integer grid pixels $(400{\times}30)$ without [0, 1] real operations. Also we apply the proposed system to the truck backer-upper control system. As a result, this system shows a real-time very high speed fuzzy control as compared as the conventional methods. This system will be applied to the real-time high-speed intelligent systems such as robot arm control.

FPGA Implementation and Measurement of ARM7 Microprocessor based on a Low-Power Method (저전력 기법을 적용한 ARM7 마이크로프로세서의 FPGA 구현 및 측정)

  • Kim Jae-Woo;Kim Young-Hun;Oh Min-Seok;Nam Ki-Hun;Lee Kwang-Youb
    • Proceedings of the IEEK Conference
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    • 2004.06b
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    • pp.423-426
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    • 2004
  • 본 논문에서는 저 전력 마이크로프로세서를 개발하기 위해 ARM7 마이크로프로세서와 명령어 호환을 갖는 32비트 RISC 구조의 마이크로프로세서를 설계하였다. 저 전력 ARM7 마이크로프로세서 IP 구현을 위하여 새로운 정수 나눗셈 명령어를 정의하고 이를 적용하는 회로를 설계하여 제수가 피제수보다 큰 경우 6.4nW, 그 이외의 경우에는 76.5 nW를 소모하여 기존의 방법보다 $140{\~}860\%$ 까지 개선되었음을 측정하였다. 또한 Multi-cycle 명령어 발생시 Prefetch에 의한 전력 소모를 줄이기 위하여 명령어의 condition code를 미리 결정함으로써 $50\%$의 prefetch 동작 횟수를 줄였다. 그 결과 저 전력 파이프라인의 경우에는 1.943mW/1MHz의 소비 전력이 측정되었다.

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