• Electrical & Electronic Materials
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• v.11 no.3
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• pp.258-263
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• 1998

• Electrical & Electronic Materials
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• v.18 no.10
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• pp.16-22
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• 2005

• Electrical & Electronic Materials
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• v.12 no.12
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• pp.1-9
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• 1999

• Journal of Broadcast Engineering
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• v.26 no.6
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• pp.748-757
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• 2021

In this paper, we propose a gaze estimation network in which eye landmark position detection and gaze direction vector estimation are integrated into one deep learning network. The proposed network uses the Stacked Hourglass Network as a backbone structure and is largely composed of three parts: a landmark detector, a feature map extractor, and a gaze direction estimator. The landmark detector estimates the coordinates of 50 eye landmarks, and the feature map extractor generates a feature map of the eye image for estimating the gaze direction. And the gaze direction estimator estimates the final gaze direction vector by combining each output result. The proposed network was trained using virtual synthetic eye images and landmark coordinate data generated through the UnityEyes dataset, and the MPIIGaze dataset consisting of real human eye images was used for performance evaluation. Through the experiment, the gaze estimation error showed a performance of 3.9, and the estimation speed of the network was 42 FPS (Frames per second).

• Journal of Radiation Protection and Research
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• v.39 no.2
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• pp.81-88
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• 2014

Recently, a new imaging method, gamma vertex imaging (GVI), was proposed for the verification of in-vivo proton dose distribution. In GVI, the vertices of prompt gammas generated by proton induced nuclear interaction were determined by tracking the Compton-recoiled electrons. The GVI system is composed of a beryllium electron converter for converting gamma to electron, two double-sided silicon strip detectors (DSSDs) for the electron tracking, and a scintillation detector for the energy determination of the electron. In the present study, the modules of a charge sensitive preamplifier (CSP) and a shaping amplifier for the analog signal processing of DSSD were developed and the performances were evaluated by comparing the energy resolutions with those of the commercial products. Based on the results, it was confirmed that the energy resolution of the developed CSP module was a little lower than that of the CR-113 (Cremat, Inc., MA), and the resolution of the shaping amplifier was similar to that of the CR-200 (Cremat, Inc., MA). The value of $V_{rms}$ representing the magnitude of noise of the developed system was estimated as 6.48 keV and it was confirmed that the trajectory of the electron can be measured by the developed system considering the minimum energy deposition ( > ~51 keV) of Compton-recoiled electron in 145-${\mu}m$-thick DSSD.

• Transactions of the Korean Society of Machine Tool Engineers
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• v.17 no.4
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• pp.15-21
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• 2008

Secondary electron detectors used in scanning electron microscope accept secondary electrons emitted from the specimen and convert them to an electrical signal that, after amplification, is used to modulate the gray-level intensities on a cathode ray tube, producing an image of the specimen. In order to acquire images with good qualities, as many secondary electrons as possible should be reached to the detector. To realize this it is very important to select an appropriate mounting position and angle of the detector inside the chamber of scanning electron microscope. In this paper, a number of numerical simulations are performed to explore the relationships between detection rates of secondary electrons and the values of some parameters, such as distances between the detector and sample, relative mounting positions of scintillator positioned inside the detector with respect to detector cover, two types of mounting angles of the detector. The relationships between detection rates and applied voltages to corona ring and faraday cage, and energies of secondary electrons are investigated as well.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.5
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• pp.242-250
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• 2013

In this paper, R-wave detection algorithm using refractory period to reflect the depolarization and repolarization of the myocardial cells of the heart is proposed. The proposed algorithm detects R-peaks using the features of R-wave and variable refractory period. First, the proposed algorithm extracts candidate R-peaks that have a relatively high potential and calculates the refractory period based on the kurtosis and potential for candidate R-peaks. Next, R-peak is determined by morphological features of the R-wave within the refractory period. In addition, due to less computation in the proposed algorithm, real-time processing is possible. The algorithm is applied to all records of the MIT-BIH arrhythmia database and the obtained results show a competitive detection rate of over 99.7%.

• Electronics and Telecommunications Trends
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• v.18 no.2 s.80
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• pp.99-109
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• 2003

검출된 소프트웨어의 결함에 대한 분석은 소프트웨어의 품질을 향상시키기 위한 여러 활동에 많은 도움을 주고 있다. 특히 개발중인 소프트웨어 컴포넌트들에 대한 검출된 결함 분석은 개발기간에 소프트웨어내에 숨어있는 결함(latent defect)에 초점이 맞추어져 시험에 많은 도움을 주고 있다. 본 논문은 대형 교환 소프트웨어로부터 시험에서 검출된 결함 데이터를 이용하여 소프트웨어의 특성을 조사, 분석하여 이를 시험에 활용하고 시험의 효율성과 시험효과에 대한 가이드 라인을 제안한다.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.432-432
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• 2013

현대에 이르러 직접방식 엑스선 검출기에서는 기존의 a-Se을 주로 이용하였지만, 고전압 인가에 따른 회로 손상과 짧은 수명, 그리고 누설전류에 따른 안전의 문제 등으로 낮은 에너지 밴드갭과 높은 흡수효율, 비저항 등에 의거한 다양한 대체 물질에 대한 연구가 활발하게 이루어져가고 있다. 본 논문에서는 직접방식 엑스선 검출물질로 전기이동도와 흡수효율이 뛰어나고, 밴드갭이 낮아 태양전지분야 뿐만 아니라 최근 엑스선 검출물질로 각광받고 있는 CdTe를 선정하였다. 연구의 목적은 PVD (Physical Vapor Deposition)방식의 CdTe 검출 물질의 제작과정에서 CdTe가 기화되어 하부전극 기판에 증착될 시, 하부전극 기판 온도에 따른 CdTe의 박막형성과 전기적 측정을 실시하여 그에 따른 최적의 증착조건을 선정하는 것이다. 하부전극 기판으로는 Au/glass를 사용하였으며 증착 시, $200^{\circ}C$, $300^{\circ}C$, $400^{\circ}C$로 나누어 특성을 평가하였다. 시료는 파우더형태의 다결정CdTe를 120 g를 사용하여 증착완료 시, 약 $100{\mu}m$의 박막두께를 구현하였다. PVD증착의 조건으로는 Mo재질의 보트를 사용하였으며, 증착 시 진공도는 $5{\times}10^{-6}$ Torr, 보트온도는 약 $350^{\circ}C$ 소요시간은 5시간이었다. 증착이 완료된 CdTe의 표면구조와 전기적 특성평가를 위해 SEM촬영을 실시하였고, 전기적 특성 평가를 위해 CdTe표면에 Au를 PVD방식으로 증착하였다. 실험 결과 SEM촬영을 이용한 표면특성에서는 하부전극 기판의 온도가 높아질수록 표면 결정입자가 증가하는 것을 확인할 수 있었으며, 전기적 특성에서도 하부전극 기판의 온도가 증가할수록 RQA-5 조건의 70 kVp, 100 mA, 0.03 sec 엑스선에 대한 우수한 민감도와 암전류 값을 확인하였다. 이러한 결과는 증착과정에서 온도에 따른 다결정 CdTe의 표면결정 크기 증가는 동일한 면적에서 표면결정 수의 감소를 뜻한다. 이는 결정간의 경계에서 트랩 되어지는 전자가 감소하고, 전자의 이동도 또한 높은 효율을 나타냄을 확인할 수 있었다. 따라서 본 연구를 통하여 CdTe기반의 직접방식 엑스선 검출기 제작과정에서 증착 시 하부전극기판 온도가 증가할수록 결정의 크기가 증가하여 최적의 전기적 특성을 나타냄을 검증할 수 있었다.

• Journal of IKEEE
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• v.8 no.1 s.14
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• pp.12-21
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• 2004

Error control is one of major concerns in many electronic systems. Experience shows that most malfunctions during system operation are caused by transient faults, which often mean abnormal signal delays that may result in violations of circuit element timing constraints. This paper presents a novel CMOS-based concurrent timing error detector that makes a flip-flop to sense and then signal whether its data has been potentially corrupted or not by a setup or hold timing violation. Designed circuit performs a quiescent supply current evaluation to determine timing violation from the input changes in relation to a clock edge. If the input is too close to the clock time, the resulting switching transient current in the detection circuit exceeds a reference threshold at the instant of the clock transition and an error is flagged. The circuit is designed with a $0.25{\mu}m$ standard CMOS technology at a 2.5 V supply voltage. The validity and effectiveness are verified through the HSPICE simulation. The simulation results in this paper shows that designed circuit can be used to detect setup and hold time violations effectively in clocked circuit element.