• Journal of Yeungnam Medical Science
• /
• v.18 no.1
• /
• pp.39-50
• /
• 2001

Background: Power spectrum analysis method is a powerful noninvasive tool for quantifying autonomic nervous system activity. In this paper, we developed a data acquistion system for estimating the activity of the autonomic nervous system by the analysis of heart rate and respiratory rate variability using power spectrum analysis. Materials and methods: For the detection of QRS peak and measurement of respiratory rate from patient's ECG, we used low-pass filter and impedence method respectively. This system adopt an isolated power for patient's safety. In this system, two output signals can be obtained: R-R interval heart rate) and respiration rate time series. Experimental ranges are 30-240 BPM for ECG and 15-80 BPM for respiration. Results: The system can acquire two signals accurately both in the experimental test using simulator and in real clinical setting. Conclusion: The system developed in this paper is efficient for the acquisition of heart rate and respiration signals. This system will play a role in research area for improving our understanding of the pathophysiologic involvement of the autonomic nervous system in various disease states.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.46 no.3
• /
• pp.60-68
• /
• 2009

This work proposes a 10b 200MS/s 65nm CMOS ADC for high-definition video systems such as HDTV requiring high resolution and fast operating speed simultaneously. The proposed ADC employs a four-step pipeline architecture to minimize power consumption and chip area. The input SHA based on four capacitors reduces the output signal range from $1.4V_{p-p}$ to $1.0V_{p-p}$ considering high input signal levels at a low supply voltage of 1.2V. The proposed three-stage amplifiers in the input SHA and MDAC1 overcome the low output resistance problem as commonly observed in a 65nm CMOS process. The proposed multipath frequency-compensation technique enables the conventional RNMC based three-stage amplifiers to achieve a stable operation at a high sampling rate of 200MS/s. The conventional switched-bias power-reduction technique in the sub-ranging flash ADCs further reduces power consumption while the reference generator integrated on chip with optional off-chip reference voltages allows versatile system a locations. The prototype ADC in a 65nm CMOS technology demonstrates a measured DNL and INL within 0.19LSB and 0.61LSB, respectively. The ADC shows a maximum SNDR of 54.BdB and 52.4dB and a maximum SFDR of 72.9dB and 64.8dB at 150MS/S and 200MS/s, respectively. The proposed ADC occupies an active die area of $0.76mm^2$ and consumes 75.6mW at a 1.2V supply voltage.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.46 no.3
• /
• pp.75-85
• /
• 2009

This work proposes a 13b 100MS/s 0.13um CMOS ADC for 3G communication systems such as two-carrier W-CDMA applications simultaneously requiring high resolution, low power, and small size at high speed. The proposed ADC employs a four-step pipeline architecture to optimize power consumption and chip area at the target resolution and sampling rate. Area-efficient high-speed high-resolution gate-bootstrapping circuits are implemented at the sampling switches of the input SHA to maintain signal linearity over the Nyquist rate even at a 1.0V supply operation. The cascode compensation technique on a low-impedance path implemented in the two-stage amplifiers of the SHA and MDAC simultaneously achieves the required operation speed and phase margin with more reduced power consumption than the Miller compensation technique. Low-glitch dynamic latches in sub-ranging flash ADCs reduce kickback-noise referred to the differential input stage of the comparator by isolating the input stage from output nodes to improve system accuracy. The proposed low-noise current and voltage references based on triple negative T.C. circuits are employed on chip with optional off-chip reference voltages. The prototype ADC in a 0.13um 1P8M CMOS technology demonstrates the measured DNL and INL within 0.70LSB and 1.79LSB, respectively. The ADC shows a maximum SNDR of 64.5dB and a maximum SFDR of 78.0dB at 100MS/s, respectively. The ABC with an active die area of $1.22mm^2$ consumes 42.0mW at 100MS/s and a 1.2V supply, corresponding to a FOM of 0.31pJ/conv-step.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.22 no.6
• /
• pp.599-609
• /
• 2021

A novel grounding system, which is presented in IEC 60364, has been adopted since 2021. A safety evaluation for the human body on the grounding system is required due to the various characteristics of the touch voltage and current passing when the human body experiences an electric shock. The Korea Electrical Safety Corporation (KESCO) and Korea Electric Association (KEA) have been conducting a safety technical education on the grounding system. On the other hand, it is difficult to instruct the electrical safety manager because of a lack of safety evaluations for the test equipment on the grounding system. Therefore, this paper modeled and implemented a test device for a safety evaluation depending on the grounding system of IEC 60364. Namely, this paper presents the modeling of the test device for a safety evaluation using PSCAD/EMTDC S/W, which is composed of an AC grid section, s test device section on the grounding system, and a sub-device section. This paper implemented a test device for safety evaluation, which consisted of an AC grid section, TT grounding system section, TN-S grounding system section, and monitoring section. From the simulation and test results with the safety characteristics of the human body in the TT and TN-S grounding system, when the fault impedances are 0[Ω], 10[Ω], and 100[Ω], the currents passing through the human body in the TT grounding system are 104[mA], 87.4[mA], and 35.5[mA], respectively. The corresponding currents in the TN-S grounding system are 54.9[mA], 4.1[mA], and 0.4[mA], respectively. Based on the results, the protection performance for an electric shock to the human body in the TN-S system is better than the TT system. This can be improved when the existing grounding system is changed from the TT system to the TN-S system.